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@@ -0,0 +1,102 @@
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+Broadcom Northstar2 IOMUX Controller
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+
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+The Northstar2 IOMUX controller supports group based mux configuration. There
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+are some individual pins that support modifying the pinconf parameters.
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+
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+Required properties:
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+
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+- compatible:
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+ Must be "brcm,ns2-pinmux"
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+
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+- reg:
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+ Define the base and range of the I/O address space that contains the
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+ Northstar2 IOMUX and pin configuration registers.
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+
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+Properties in sub nodes:
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+
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+- function:
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+ The mux function to select
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+
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+- groups:
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+ The list of groups to select with a given function
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+
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+- pins:
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+ List of pin names to change configuration
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+
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+The generic properties bias-disable, bias-pull-down, bias-pull-up,
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+drive-strength, slew-rate, input-enable, input-disable are supported
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+for some individual pins listed at the end.
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+
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+For more details, refer to
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+Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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+
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+For example:
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+
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+ pinctrl: pinctrl@6501d130 {
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+ compatible = "brcm,ns2-pinmux";
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+ reg = <0x6501d130 0x08>,
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+ <0x660a0028 0x04>,
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+ <0x660009b0 0x40>;
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&nand_sel &uart3_rx &sdio0_d4>;
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+
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+ /* Select nand function */
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+ nand_sel: nand_sel {
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+ function = "nand";
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+ groups = "nand_grp";
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+ };
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+
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+ /* Pull up the uart3 rx pin */
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+ uart3_rx: uart3_rx {
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+ pins = "uart3_sin";
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+ bias-pull-up;
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+ };
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+
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+ /* Set the drive strength of sdio d4 pin */
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+ sdio0_d4: sdio0_d4 {
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+ pins = "sdio0_data4";
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+ drive-strength = <8>;
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+ };
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+ };
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+
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+List of supported functions and groups in Northstar2:
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+
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+"nand": "nand_grp"
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+
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+"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp",
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+ "nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp",
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+ "nor_addr_12_15_grp"
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+
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+"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp",
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+ "gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp",
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+ "gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp",
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+ "gpio_28_29_grp", "gpio_30_31_grp"
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+
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+"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp",
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+ "pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp"
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+
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+"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp"
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+
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+"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp",
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+ "uart1_rts_cts_grp", "uart1_in_out_grp"
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+
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+"uart2": "uart2_rts_cts_grp"
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+
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+"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp"
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+
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+
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+List of pins that support pinconf parameters:
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+
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+"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout",
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+"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck",
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+"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7",
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+"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4",
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+"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1",
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+"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk",
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+"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1",
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+"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk",
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+"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc",
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+"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent",
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+"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc",
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+"usb2_overcurrent", "sata_led1", "sata_led0"
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Yendapally Reddy Dhananjaya Reddy