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@@ -715,15 +715,33 @@ static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
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*/
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static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
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{
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- u8 bit;
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unsigned long edac_cap = EDAC_FLAG_NONE;
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+ u8 bit;
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- bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
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- ? 19
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- : 17;
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+ if (pvt->umc) {
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+ u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
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- if (pvt->dclr0 & BIT(bit))
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- edac_cap = EDAC_FLAG_SECDED;
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+ for (i = 0; i < NUM_UMCS; i++) {
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+ if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
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+ continue;
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+
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+ umc_en_mask |= BIT(i);
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+
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+ /* UMC Configuration bit 12 (DimmEccEn) */
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+ if (pvt->umc[i].umc_cfg & BIT(12))
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+ dimm_ecc_en_mask |= BIT(i);
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+ }
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+
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+ if (umc_en_mask == dimm_ecc_en_mask)
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+ edac_cap = EDAC_FLAG_SECDED;
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+ } else {
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+ bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
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+ ? 19
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+ : 17;
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+
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+ if (pvt->dclr0 & BIT(bit))
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+ edac_cap = EDAC_FLAG_SECDED;
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+ }
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return edac_cap;
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}
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