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@@ -363,6 +363,7 @@
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#define EEE_NWAY_EN 0x1000
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#define TX_QUIET_EN 0x0200
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#define RX_QUIET_EN 0x0100
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+#define sd_rise_time_mask 0x0070
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#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
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#define RG_RXLPI_MSK_HFDUP 0x0008
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#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
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@@ -375,6 +376,7 @@
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#define RG_EEEPRG_EN 0x0010
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/* OCP_EEE_CONFIG3 */
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+#define fast_snr_mask 0xff80
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#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
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#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
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#define MSK_PH 0x0006 /* bit 0 ~ 3 */
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@@ -2950,43 +2952,92 @@ static int rtl8152_close(struct net_device *netdev)
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return res;
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}
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-static void r8152b_enable_eee(struct r8152 *tp)
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+static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
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+{
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+ ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
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+ ocp_reg_write(tp, OCP_EEE_DATA, reg);
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+ ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
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+}
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+
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+static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
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+{
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+ u16 data;
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+
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+ r8152_mmd_indirect(tp, dev, reg);
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+ data = ocp_reg_read(tp, OCP_EEE_DATA);
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+ ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
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+
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+ return data;
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+}
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+
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+static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
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{
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+ r8152_mmd_indirect(tp, dev, reg);
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+ ocp_reg_write(tp, OCP_EEE_DATA, data);
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+ ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
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+}
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+
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+static void r8152_eee_en(struct r8152 *tp, bool enable)
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+{
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+ u16 config1, config2, config3;
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u32 ocp_data;
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ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
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- ocp_data |= EEE_RX_EN | EEE_TX_EN;
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+ config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
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+ config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
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+ config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
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+
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+ if (enable) {
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+ ocp_data |= EEE_RX_EN | EEE_TX_EN;
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+ config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
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+ config1 |= sd_rise_time(1);
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+ config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
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+ config3 |= fast_snr(42);
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+ } else {
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+ ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
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+ config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
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+ RX_QUIET_EN);
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+ config1 |= sd_rise_time(7);
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+ config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
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+ config3 |= fast_snr(511);
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+ }
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+
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ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
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- ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
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- EEE_10_CAP | EEE_NWAY_EN |
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- TX_QUIET_EN | RX_QUIET_EN |
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- sd_rise_time(1) | RG_RXLPI_MSK_HFDUP |
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- SDFALLTIME);
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- ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
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- RG_LDVQUIET_EN | RG_CKRSEL |
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- RG_EEEPRG_EN);
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- ocp_reg_write(tp, OCP_EEE_CONFIG3, fast_snr(42) | RG_LFS_SEL | MSK_PH);
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- ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | MDIO_MMD_AN);
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- ocp_reg_write(tp, OCP_EEE_DATA, MDIO_AN_EEE_ADV);
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- ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | MDIO_MMD_AN);
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- ocp_reg_write(tp, OCP_EEE_DATA, MDIO_EEE_100TX);
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- ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
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+ ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
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+ ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
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+ ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
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}
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-static void r8153_enable_eee(struct r8152 *tp)
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+static void r8152b_enable_eee(struct r8152 *tp)
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+{
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+ r8152_eee_en(tp, true);
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+ r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
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+}
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+
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+static void r8153_eee_en(struct r8152 *tp, bool enable)
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{
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u32 ocp_data;
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- u16 data;
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+ u16 config;
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ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
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- ocp_data |= EEE_RX_EN | EEE_TX_EN;
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+ config = ocp_reg_read(tp, OCP_EEE_CFG);
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+
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+ if (enable) {
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+ ocp_data |= EEE_RX_EN | EEE_TX_EN;
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+ config |= EEE10_EN;
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+ } else {
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+ ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
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+ config &= ~EEE10_EN;
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+ }
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+
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ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
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- data = ocp_reg_read(tp, OCP_EEE_CFG);
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- data |= EEE10_EN;
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- ocp_reg_write(tp, OCP_EEE_CFG, data);
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- data = ocp_reg_read(tp, OCP_EEE_ADV);
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- data |= MDIO_EEE_1000T | MDIO_EEE_100TX;
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- ocp_reg_write(tp, OCP_EEE_ADV, data);
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+ ocp_reg_write(tp, OCP_EEE_CFG, config);
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+}
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+
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+static void r8153_enable_eee(struct r8152 *tp)
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+{
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+ r8153_eee_en(tp, true);
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+ ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
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}
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static void r8152b_enable_fc(struct r8152 *tp)
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