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@@ -8,6 +8,7 @@
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* Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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+ * Copyright(c) 2018 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@@ -35,6 +36,7 @@
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* Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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+ * Copyright(c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -73,6 +75,7 @@
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#include <linux/gfp.h>
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#include <linux/vmalloc.h>
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#include <linux/pm_runtime.h>
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+#include <linux/module.h>
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#include "iwl-drv.h"
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#include "iwl-trans.h"
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@@ -179,7 +182,8 @@ out:
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static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
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{
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/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
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- iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
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+ iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
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+ BIT(trans->cfg->csr->flag_sw_reset));
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usleep_range(5000, 6000);
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}
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@@ -372,7 +376,8 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
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* Set "initialization complete" bit to move adapter from
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* D0U* --> D0A* (powered-up active) state.
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*/
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- iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ iwl_set_bit(trans, CSR_GP_CNTRL,
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+ BIT(trans->cfg->csr->flag_init_done));
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/*
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* Wait for clock stabilization; once stabilized, access to
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@@ -380,8 +385,9 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
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* and accesses to uCode SRAM.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ 25000);
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if (ret < 0) {
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IWL_ERR(trans, "Failed to init the card\n");
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return ret;
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@@ -459,15 +465,16 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
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* Set "initialization complete" bit to move adapter from
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* D0U* --> D0A* (powered-up active) state.
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*/
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- iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ iwl_set_bit(trans, CSR_GP_CNTRL,
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+ BIT(trans->cfg->csr->flag_init_done));
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/*
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* Wait for clock stabilization; once stabilized, access to
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* device-internal resources is possible.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (WARN_ON(ret < 0)) {
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IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
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@@ -519,7 +526,7 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
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* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
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*/
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ BIT(trans->cfg->csr->flag_init_done));
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/* Activates XTAL resources monitor */
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__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
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@@ -541,11 +548,12 @@ void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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int ret;
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/* stop device's busmaster DMA activity */
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- iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
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+ iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
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+ BIT(trans->cfg->csr->flag_stop_master));
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- ret = iwl_poll_bit(trans, CSR_RESET,
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- CSR_RESET_REG_FLAG_MASTER_DISABLED,
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- CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
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+ ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset,
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+ BIT(trans->cfg->csr->flag_master_dis),
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+ BIT(trans->cfg->csr->flag_master_dis), 100);
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if (ret < 0)
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IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
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@@ -594,7 +602,7 @@ static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
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* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
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*/
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ BIT(trans->cfg->csr->flag_init_done));
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}
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static int iwl_pcie_nic_init(struct iwl_trans *trans)
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@@ -1267,7 +1275,7 @@ static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
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/* Make sure (redundant) we've released our request to stay awake */
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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/* Stop the device, and put it in low power state */
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iwl_pcie_apm_stop(trans, false);
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@@ -1497,9 +1505,9 @@ static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
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iwl_pcie_synchronize_irqs(trans);
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ BIT(trans->cfg->csr->flag_init_done));
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iwl_pcie_enable_rx_wake(trans, false);
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@@ -1543,15 +1551,17 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
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iwl_pcie_reset_ict(trans);
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iwl_enable_interrupts(trans);
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- iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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- iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ iwl_set_bit(trans, CSR_GP_CNTRL,
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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+ iwl_set_bit(trans, CSR_GP_CNTRL,
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+ BIT(trans->cfg->csr->flag_init_done));
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if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
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udelay(2);
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (ret < 0) {
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IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
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@@ -1562,7 +1572,7 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
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if (!reset) {
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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} else {
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iwl_trans_pcie_tx_reset(trans);
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@@ -1926,6 +1936,29 @@ static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
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clear_bit(STATUS_TPOWER_PMI, &trans->status);
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}
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+struct iwl_trans_pcie_removal {
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+ struct pci_dev *pdev;
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+ struct work_struct work;
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+};
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+
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+static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
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+{
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+ struct iwl_trans_pcie_removal *removal =
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+ container_of(wk, struct iwl_trans_pcie_removal, work);
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+ struct pci_dev *pdev = removal->pdev;
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+ char *prop[] = {"EVENT=INACCESSIBLE", NULL};
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+
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+ dev_err(&pdev->dev, "Device gone - attempting removal\n");
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+ kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
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+ pci_lock_rescan_remove();
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+ pci_dev_put(pdev);
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+ pci_stop_and_remove_bus_device(pdev);
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+ pci_unlock_rescan_remove();
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+
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+ kfree(removal);
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+ module_put(THIS_MODULE);
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+}
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+
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static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
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unsigned long *flags)
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{
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@@ -1939,7 +1972,7 @@ static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
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/* this bit wakes up the NIC */
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__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
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udelay(2);
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@@ -1964,15 +1997,59 @@ static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
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* and do not save/restore SRAM when power cycling.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
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- (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
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+ BIT(trans->cfg->csr->flag_val_mac_access_en),
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+ (BIT(trans->cfg->csr->flag_mac_clock_ready) |
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CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
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if (unlikely(ret < 0)) {
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- iwl_trans_pcie_dump_regs(trans);
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- iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
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+ u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
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+
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WARN_ONCE(1,
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"Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
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- iwl_read32(trans, CSR_GP_CNTRL));
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+ cntrl);
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+
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+ iwl_trans_pcie_dump_regs(trans);
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+
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+ if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
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+ struct iwl_trans_pcie_removal *removal;
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+
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+ if (trans_pcie->scheduled_for_removal)
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+ goto err;
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+
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+ IWL_ERR(trans, "Device gone - scheduling removal!\n");
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+
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+ /*
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+ * get a module reference to avoid doing this
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+ * while unloading anyway and to avoid
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+ * scheduling a work with code that's being
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+ * removed.
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+ */
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+ if (!try_module_get(THIS_MODULE)) {
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+ IWL_ERR(trans,
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+ "Module is being unloaded - abort\n");
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+ goto err;
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+ }
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+
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+ removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
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+ if (!removal) {
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+ module_put(THIS_MODULE);
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+ goto err;
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+ }
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+ /*
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+ * we don't need to clear this flag, because
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+ * the trans will be freed and reallocated.
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+ */
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+ trans_pcie->scheduled_for_removal = true;
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+
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+ removal->pdev = to_pci_dev(trans->dev);
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+ INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
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+ pci_dev_get(removal->pdev);
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+ schedule_work(&removal->work);
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+ } else {
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+ iwl_write32(trans, CSR_RESET,
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+ CSR_RESET_REG_FLAG_FORCE_NMI);
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+ }
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+
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+err:
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spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
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return false;
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}
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@@ -2003,7 +2080,7 @@ static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
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goto out;
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__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ BIT(trans->cfg->csr->flag_mac_access_req));
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/*
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* Above we read the CSR_GP_CNTRL register, which will flush
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* any previous writes, but we need the write that clears the
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@@ -3232,12 +3309,12 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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* id located at the AUX bus MISC address space.
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*/
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iwl_set_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+ BIT(trans->cfg->csr->flag_init_done));
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udelay(2);
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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- CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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+ BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (ret < 0) {
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IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
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