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@@ -158,6 +158,14 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
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POSTING_READ(fence_reg_lo);
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}
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+static void _clear_vgpu_fence(struct intel_vgpu *vgpu)
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+{
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+ int i;
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+
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+ for (i = 0; i < vgpu_fence_sz(vgpu); i++)
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+ intel_vgpu_write_fence(vgpu, i, 0);
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+}
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+
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static void free_vgpu_fence(struct intel_vgpu *vgpu)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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@@ -171,9 +179,9 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu)
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intel_runtime_pm_get(dev_priv);
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mutex_lock(&dev_priv->drm.struct_mutex);
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+ _clear_vgpu_fence(vgpu);
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for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
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reg = vgpu->fence.regs[i];
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- intel_vgpu_write_fence(vgpu, i, 0);
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list_add_tail(®->link,
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&dev_priv->mm.fence_list);
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}
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@@ -201,13 +209,14 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
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continue;
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list_del(pos);
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vgpu->fence.regs[i] = reg;
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- intel_vgpu_write_fence(vgpu, i, 0);
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if (++i == vgpu_fence_sz(vgpu))
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break;
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}
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if (i != vgpu_fence_sz(vgpu))
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goto out_free_fence;
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+ _clear_vgpu_fence(vgpu);
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+
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mutex_unlock(&dev_priv->drm.struct_mutex);
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intel_runtime_pm_put(dev_priv);
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return 0;
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@@ -306,6 +315,22 @@ void intel_vgpu_free_resource(struct intel_vgpu *vgpu)
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free_resource(vgpu);
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}
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+/**
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+ * intel_vgpu_reset_resource - reset resource state owned by a vGPU
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+ * @vgpu: a vGPU
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+ *
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+ * This function is used to reset resource state owned by a vGPU.
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+ *
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+ */
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+void intel_vgpu_reset_resource(struct intel_vgpu *vgpu)
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+{
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+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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+
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+ intel_runtime_pm_get(dev_priv);
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+ _clear_vgpu_fence(vgpu);
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+ intel_runtime_pm_put(dev_priv);
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+}
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+
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/**
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* intel_alloc_vgpu_resource - allocate HW resource for a vGPU
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* @vgpu: vGPU
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