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@@ -22,6 +22,8 @@
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#define DA8XX_USB0_BASE 0x01e00000
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#define DA8XX_USB1_BASE 0x01e25000
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+static struct clk *usb20_clk;
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+
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static struct platform_device da8xx_usb_phy = {
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.name = "da8xx-usb-phy",
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.id = -1,
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@@ -158,26 +160,13 @@ int __init da8xx_register_usb_refclkin(int rate)
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static void usb20_phy_clk_enable(struct clk *clk)
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{
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- struct clk *usb20_clk;
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- int err;
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u32 val;
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u32 timeout = 500000; /* 500 msec */
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val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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- usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
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- if (IS_ERR(usb20_clk)) {
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- pr_err("could not get usb20 clk: %ld\n", PTR_ERR(usb20_clk));
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- return;
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- }
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-
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/* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */
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- err = clk_prepare_enable(usb20_clk);
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- if (err) {
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- pr_err("failed to enable usb20 clk: %d\n", err);
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- clk_put(usb20_clk);
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- return;
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- }
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+ davinci_clk_enable(usb20_clk);
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/*
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* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
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@@ -197,8 +186,7 @@ static void usb20_phy_clk_enable(struct clk *clk)
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pr_err("Timeout waiting for USB 2.0 PHY clock good\n");
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done:
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- clk_disable_unprepare(usb20_clk);
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- clk_put(usb20_clk);
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+ davinci_clk_disable(usb20_clk);
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}
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static void usb20_phy_clk_disable(struct clk *clk)
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@@ -285,11 +273,19 @@ static struct clk_lookup usb20_phy_clk_lookup =
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int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin)
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{
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struct clk *parent;
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- int ret = 0;
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+ int ret;
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+
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+ usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
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+ ret = PTR_ERR_OR_ZERO(usb20_clk);
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+ if (ret)
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+ return ret;
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parent = clk_get(NULL, use_usb_refclkin ? "usb_refclkin" : "pll0_aux");
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- if (IS_ERR(parent))
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- return PTR_ERR(parent);
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+ ret = PTR_ERR_OR_ZERO(parent);
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+ if (ret) {
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+ clk_put(usb20_clk);
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+ return ret;
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+ }
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usb20_phy_clk.parent = parent;
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ret = clk_register(&usb20_phy_clk);
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