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@@ -350,13 +350,13 @@ static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
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}
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static void xgpu_vi_mailbox_trans_msg(struct amdgpu_device *adev,
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- enum idh_event event)
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+ enum idh_request req)
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{
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u32 reg;
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reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);
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reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,
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- MSGBUF_DATA, event);
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+ MSGBUF_DATA, req);
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WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);
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xgpu_vi_mailbox_set_valid(adev, true);
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@@ -458,20 +458,20 @@ static int xgpu_vi_request_reset(struct amdgpu_device *adev)
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static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev,
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bool init)
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{
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- enum idh_event event;
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+ enum idh_request req;
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- event = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
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- return xgpu_vi_send_access_requests(adev, event);
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+ req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
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+ return xgpu_vi_send_access_requests(adev, req);
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}
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static int xgpu_vi_release_full_gpu_access(struct amdgpu_device *adev,
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bool init)
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{
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- enum idh_event event;
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+ enum idh_request req;
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int r = 0;
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- event = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
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- r = xgpu_vi_send_access_requests(adev, event);
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+ req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
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+ r = xgpu_vi_send_access_requests(adev, req);
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return r;
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}
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