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@@ -5462,6 +5462,7 @@ static void gfx_v8_0_inactive_hqd(struct amdgpu_device *adev,
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{
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int i;
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+ mutex_lock(&adev->srbm_mutex);
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vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
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if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
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WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, 2);
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@@ -5471,6 +5472,8 @@ static void gfx_v8_0_inactive_hqd(struct amdgpu_device *adev,
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udelay(1);
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}
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}
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+ vi_srbm_select(adev, 0, 0, 0, 0);
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+ mutex_unlock(&adev->srbm_mutex);
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}
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static int gfx_v8_0_pre_soft_reset(void *handle)
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@@ -5576,11 +5579,13 @@ static int gfx_v8_0_soft_reset(void *handle)
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static void gfx_v8_0_init_hqd(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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+ mutex_lock(&adev->srbm_mutex);
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vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
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WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
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WREG32(mmCP_HQD_PQ_RPTR, 0);
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WREG32(mmCP_HQD_PQ_WPTR, 0);
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vi_srbm_select(adev, 0, 0, 0, 0);
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+ mutex_unlock(&adev->srbm_mutex);
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}
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static int gfx_v8_0_post_soft_reset(void *handle)
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