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@@ -4485,7 +4485,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val, cmd;
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- WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
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+ WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
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dev_priv->vlv_cdclk_freq = cdclk;
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if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
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@@ -4542,24 +4542,6 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
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intel_i2c_reset(dev);
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}
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-int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
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-{
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- int cur_cdclk, vco;
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- int divider;
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-
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- vco = valleyview_get_vco(dev_priv);
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-
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- mutex_lock(&dev_priv->dpio_lock);
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- divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
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- mutex_unlock(&dev_priv->dpio_lock);
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-
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- divider &= DISPLAY_FREQUENCY_VALUES;
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-
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- cur_cdclk = DIV_ROUND_CLOSEST(vco << 1, divider + 1);
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-
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- return cur_cdclk;
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-}
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-
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static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
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int max_pixclk)
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{
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@@ -5269,7 +5251,18 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
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static int valleyview_get_display_clock_speed(struct drm_device *dev)
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{
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- return 400000; /* FIXME */
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ int vco = valleyview_get_vco(dev_priv);
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+ u32 val;
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+ int divider;
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+
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+ mutex_lock(&dev_priv->dpio_lock);
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+ val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
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+ mutex_unlock(&dev_priv->dpio_lock);
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+
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+ divider = val & DISPLAY_FREQUENCY_VALUES;
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+
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+ return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
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}
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static int i945_get_display_clock_speed(struct drm_device *dev)
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