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@@ -378,6 +378,7 @@ struct msdc_host {
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u32 sclk; /* SD/MS bus clock frequency */
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unsigned char timing;
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bool vqmmc_enabled;
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+ u32 latch_ck;
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u32 hs400_ds_delay;
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u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
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u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
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@@ -1661,6 +1662,8 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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u32 tune_reg = host->dev_comp->pad_tune_reg;
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int i, ret;
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+ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
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+ host->latch_ck);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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@@ -1773,6 +1776,9 @@ static const struct mmc_host_ops mt_msdc_ops = {
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static void msdc_of_property_parse(struct platform_device *pdev,
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struct msdc_host *host)
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{
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+ of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
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+ &host->latch_ck);
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+
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of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
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&host->hs400_ds_delay);
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