|
@@ -238,14 +238,6 @@ static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
|
|
|
S3C2410_UDC_EP0_CSR_REG);
|
|
|
}
|
|
|
|
|
|
-static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
|
|
|
-{
|
|
|
- udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
|
|
|
- udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
|
|
|
- | S3C2410_UDC_EP0_CSR_SSE),
|
|
|
- S3C2410_UDC_EP0_CSR_REG);
|
|
|
-}
|
|
|
-
|
|
|
static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
|
|
|
{
|
|
|
udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
|
|
@@ -291,18 +283,6 @@ static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
|
|
|
}
|
|
|
}
|
|
|
|
|
|
-static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
|
|
|
-{
|
|
|
- unsigned i;
|
|
|
-
|
|
|
- /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
|
|
|
- * fifos, and pending transactions mustn't be continued in any case.
|
|
|
- */
|
|
|
-
|
|
|
- for (i = 1; i < S3C2410_ENDPOINTS; i++)
|
|
|
- s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
|
|
|
-}
|
|
|
-
|
|
|
static inline int s3c2410_udc_fifo_count_out(void)
|
|
|
{
|
|
|
int tmp;
|