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@@ -55,8 +55,8 @@ static u64 notrace ep93xx_read_sched_clock(void)
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{
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u64 ret;
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- ret = __raw_readl(EP93XX_TIMER4_VALUE_LOW);
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- ret |= ((u64) (__raw_readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
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+ ret = readl(EP93XX_TIMER4_VALUE_LOW);
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+ ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
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return ret;
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}
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@@ -64,8 +64,8 @@ cycle_t ep93xx_clocksource_read(struct clocksource *c)
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{
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u64 ret;
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- ret = __raw_readl(EP93XX_TIMER4_VALUE_LOW);
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- ret |= ((u64) (__raw_readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
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+ ret = readl(EP93XX_TIMER4_VALUE_LOW);
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+ ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
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return (cycle_t) ret;
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}
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@@ -77,12 +77,12 @@ static int ep93xx_clkevt_set_next_event(unsigned long next,
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EP93XX_TIMER123_CONTROL_CLKSEL;
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/* Clear timer */
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- __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
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+ writel(tmode, EP93XX_TIMER1_CONTROL);
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/* Set next event */
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- __raw_writel(next, EP93XX_TIMER1_LOAD);
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- __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
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- EP93XX_TIMER1_CONTROL);
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+ writel(next, EP93XX_TIMER1_LOAD);
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+ writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
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+ EP93XX_TIMER1_CONTROL);
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return 0;
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}
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@@ -91,7 +91,7 @@ static void ep93xx_clkevt_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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/* Disable timer */
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- __raw_writel(0, EP93XX_TIMER1_CONTROL);
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+ writel(0, EP93XX_TIMER1_CONTROL);
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}
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static struct clock_event_device ep93xx_clockevent = {
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@@ -107,7 +107,7 @@ static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
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struct clock_event_device *evt = dev_id;
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/* Writing any value clears the timer interrupt */
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- __raw_writel(1, EP93XX_TIMER1_CLEAR);
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+ writel(1, EP93XX_TIMER1_CLEAR);
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evt->event_handler(evt);
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@@ -124,8 +124,8 @@ static struct irqaction ep93xx_timer_irq = {
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void __init ep93xx_timer_init(void)
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{
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/* Enable and register clocksource and sched_clock on timer 4 */
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- __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
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- EP93XX_TIMER4_VALUE_HIGH);
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+ writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
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+ EP93XX_TIMER4_VALUE_HIGH);
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clocksource_mmio_init(NULL, "timer4",
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EP93XX_TIMER4_RATE, 200, 40,
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ep93xx_clocksource_read);
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