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@@ -443,6 +443,19 @@ void intel_psr_enable(struct intel_dp *intel_dp)
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vlv_psr_enable_source(intel_dp);
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}
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+ /*
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+ * FIXME: Activation should happen immediately since this function
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+ * is just called after pipe is fully trained and enabled.
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+ * However on every platform we face issues when first activation
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+ * follows a modeset so quickly.
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+ * - On VLV/CHV we get bank screen on first activation
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+ * - On HSW/BDW we get a recoverable frozen screen until next
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+ * exit-activate sequence.
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+ */
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+ if (INTEL_INFO(dev)->gen < 9)
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+ schedule_delayed_work(&dev_priv->psr.work,
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+ msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
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+
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dev_priv->psr.enabled = intel_dp;
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unlock:
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mutex_unlock(&dev_priv->psr.lock);
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@@ -751,8 +764,9 @@ void intel_psr_flush(struct drm_device *dev,
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}
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if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
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- schedule_delayed_work(&dev_priv->psr.work,
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- msecs_to_jiffies(delay_ms));
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+ if (!work_busy(&dev_priv->psr.work.work))
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+ schedule_delayed_work(&dev_priv->psr.work,
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+ msecs_to_jiffies(delay_ms));
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mutex_unlock(&dev_priv->psr.lock);
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}
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