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@@ -3326,7 +3326,7 @@ static void gen6_enable_rps(struct drm_device *dev)
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struct intel_ring_buffer *ring;
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u32 rp_state_cap, hw_max, hw_min;
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u32 gt_perf_status;
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- u32 rc6vids, pcu_mbox, rc6_mask = 0;
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+ u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
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u32 gtfifodbg;
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int rc6_mode;
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int i, ret;
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@@ -3414,17 +3414,15 @@ static void gen6_enable_rps(struct drm_device *dev)
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I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
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ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
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- if (!ret) {
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- pcu_mbox = 0;
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- ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
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- if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
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- DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
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- (dev_priv->rps.max_delay & 0xff) * 50,
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- (pcu_mbox & 0xff) * 50);
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- dev_priv->rps.hw_max = pcu_mbox & 0xff;
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- }
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- } else {
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+ if (ret)
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DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
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+
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+ ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
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+ if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
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+ DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
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+ (dev_priv->rps.max_delay & 0xff) * 50,
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+ (pcu_mbox & 0xff) * 50);
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+ dev_priv->rps.hw_max = pcu_mbox & 0xff;
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}
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dev_priv->rps.power = HIGH_POWER; /* force a reset */
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