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@@ -1579,7 +1579,6 @@ static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev)
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static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
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static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
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{
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{
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- int ret = 0;
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struct cz_power_info *pi = cz_get_pi(adev);
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struct cz_power_info *pi = cz_get_pi(adev);
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if (pi->caps_sclk_ds) {
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if (pi->caps_sclk_ds) {
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@@ -1588,20 +1587,19 @@ static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
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CZ_MIN_DEEP_SLEEP_SCLK);
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CZ_MIN_DEEP_SLEEP_SCLK);
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}
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}
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- return ret;
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+ return 0;
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}
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}
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/* ?? without dal support, is this still needed in setpowerstate list*/
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/* ?? without dal support, is this still needed in setpowerstate list*/
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static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
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static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
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{
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{
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- int ret = 0;
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struct cz_power_info *pi = cz_get_pi(adev);
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struct cz_power_info *pi = cz_get_pi(adev);
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cz_send_msg_to_smc_with_parameter(adev,
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cz_send_msg_to_smc_with_parameter(adev,
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PPSMC_MSG_SetWatermarkFrequency,
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PPSMC_MSG_SetWatermarkFrequency,
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pi->sclk_dpm.soft_max_clk);
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pi->sclk_dpm.soft_max_clk);
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- return ret;
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+ return 0;
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}
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}
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static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
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static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
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@@ -1636,7 +1634,6 @@ static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev,
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static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
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static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
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{
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{
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- int ret = 0;
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struct cz_power_info *pi = cz_get_pi(adev);
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struct cz_power_info *pi = cz_get_pi(adev);
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struct cz_ps *ps = &pi->requested_ps;
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struct cz_ps *ps = &pi->requested_ps;
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@@ -1647,21 +1644,19 @@ static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
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cz_dpm_nbdpm_lm_pstate_enable(adev, true);
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cz_dpm_nbdpm_lm_pstate_enable(adev, true);
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}
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}
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- return ret;
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+ return 0;
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}
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}
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/* with dpm enabled */
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/* with dpm enabled */
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static int cz_dpm_set_power_state(struct amdgpu_device *adev)
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static int cz_dpm_set_power_state(struct amdgpu_device *adev)
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{
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{
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- int ret = 0;
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-
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cz_dpm_update_sclk_limit(adev);
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cz_dpm_update_sclk_limit(adev);
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cz_dpm_set_deep_sleep_sclk_threshold(adev);
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cz_dpm_set_deep_sleep_sclk_threshold(adev);
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cz_dpm_set_watermark_threshold(adev);
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cz_dpm_set_watermark_threshold(adev);
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cz_dpm_enable_nbdpm(adev);
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cz_dpm_enable_nbdpm(adev);
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cz_dpm_update_low_memory_pstate(adev);
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cz_dpm_update_low_memory_pstate(adev);
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- return ret;
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+ return 0;
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}
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}
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static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
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static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
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