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@@ -40,13 +40,7 @@
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#include "cgs_common.h"
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#include "polaris10_smc.h"
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#include "smu7_ppsmc.h"
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-
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-#define POLARIS10_SMC_SIZE 0x20000
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-
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-/* Microcode file is stored in this buffer */
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-#define BUFFER_SIZE 80000
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-#define MAX_STRING_SIZE 15
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-#define BUFFER_SIZETWO 131072 /* 128 *1024 */
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+#include "smu7_smumgr.h"
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#define PPPOLARIS10_TARGETACTIVITY_DFLT 50
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@@ -66,569 +60,6 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
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static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
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0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
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-/**
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-* Set the address for reading/writing the SMC SRAM space.
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-* @param smumgr the address of the powerplay hardware manager.
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-* @param smcAddress the address in the SMC RAM to access.
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-*/
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-static int polaris10_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
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-{
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- PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
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- PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
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-
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- cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr);
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- SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
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-
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- return 0;
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-}
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-
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-/**
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-* Copy bytes from SMC RAM space into driver memory.
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-*
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-* @param smumgr the address of the powerplay SMU manager.
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-* @param smc_start_address the start address in the SMC RAM to copy bytes from
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-* @param src the byte array to copy the bytes to.
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-* @param byte_count the number of bytes to copy.
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-*/
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-int polaris10_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
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-{
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- uint32_t data;
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- uint32_t addr;
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- uint8_t *dest_byte;
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- uint8_t i, data_byte[4] = {0};
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- uint32_t *pdata = (uint32_t *)&data_byte;
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-
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- PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1;);
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- PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
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-
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- addr = smc_start_address;
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-
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- while (byte_count >= 4) {
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- polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
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-
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- *dest = PP_SMC_TO_HOST_UL(data);
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-
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- dest += 1;
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- byte_count -= 4;
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- addr += 4;
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- }
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-
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- if (byte_count) {
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- polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
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- *pdata = PP_SMC_TO_HOST_UL(data);
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- /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */
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- dest_byte = (uint8_t *)dest;
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- for (i = 0; i < byte_count; i++)
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- dest_byte[i] = data_byte[i];
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- }
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-
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- return 0;
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-}
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-
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-/**
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-* Copy bytes from an array into the SMC RAM space.
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-*
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-* @param pSmuMgr the address of the powerplay SMU manager.
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-* @param smc_start_address the start address in the SMC RAM to copy bytes to.
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-* @param src the byte array to copy the bytes from.
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-* @param byte_count the number of bytes to copy.
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-*/
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-int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
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- const uint8_t *src, uint32_t byte_count, uint32_t limit)
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-{
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- int result;
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- uint32_t data = 0;
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- uint32_t original_data;
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- uint32_t addr = 0;
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- uint32_t extra_shift;
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-
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- PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1);
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- PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
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-
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- addr = smc_start_address;
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-
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- while (byte_count >= 4) {
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- /* Bytes are written into the SMC addres space with the MSB first. */
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- data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
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-
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- result = polaris10_set_smc_sram_address(smumgr, addr, limit);
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-
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- if (0 != result)
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- return result;
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-
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- cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
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-
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- src += 4;
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- byte_count -= 4;
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- addr += 4;
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- }
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-
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- if (0 != byte_count) {
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-
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- data = 0;
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-
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- result = polaris10_set_smc_sram_address(smumgr, addr, limit);
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-
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- if (0 != result)
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- return result;
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-
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-
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- original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
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-
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- extra_shift = 8 * (4 - byte_count);
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-
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- while (byte_count > 0) {
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- /* Bytes are written into the SMC addres space with the MSB first. */
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- data = (0x100 * data) + *src++;
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- byte_count--;
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- }
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-
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- data <<= extra_shift;
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-
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- data |= (original_data & ~((~0UL) << extra_shift));
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-
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- result = polaris10_set_smc_sram_address(smumgr, addr, limit);
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-
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- if (0 != result)
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- return result;
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-
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- cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
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- }
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-
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- return 0;
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-}
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-
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-
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-static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr)
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-{
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- static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
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-
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- polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
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-
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- return 0;
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-}
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-
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-/**
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-* Return if the SMC is currently running.
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-*
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-* @param smumgr the address of the powerplay hardware manager.
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-*/
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-bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
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-{
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- return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
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- && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
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-}
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-
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-static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
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-{
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- uint32_t efuse;
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-
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- efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
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- efuse &= 0x00000001;
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- if (efuse)
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- return true;
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-
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- return false;
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-}
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-
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-/**
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-* Send a message to the SMC, and wait for its response.
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-*
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-* @param smumgr the address of the powerplay hardware manager.
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-* @param msg the message to send.
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-* @return The response that came from the SMC.
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-*/
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-int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
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-{
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- int ret;
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-
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- if (!polaris10_is_smc_ram_running(smumgr))
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- return -1;
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-
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-
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- SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
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-
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- ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
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-
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- if (ret != 1)
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- printk("\n failed to send pre message %x ret is %d \n", msg, ret);
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-
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- cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
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-
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- SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
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-
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- ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
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-
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- if (ret != 1)
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- printk("\n failed to send message %x ret is %d \n", msg, ret);
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-
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- return 0;
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-}
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-
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-
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-/**
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-* Send a message to the SMC, and do not wait for its response.
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-*
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-* @param smumgr the address of the powerplay hardware manager.
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-* @param msg the message to send.
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-* @return Always return 0.
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-*/
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-int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
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-{
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- cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
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-
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- return 0;
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-}
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-
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-/**
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-* Send a message to the SMC with parameter
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-*
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-* @param smumgr: the address of the powerplay hardware manager.
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-* @param msg: the message to send.
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-* @param parameter: the parameter to send
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-* @return The response that came from the SMC.
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-*/
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-int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
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-{
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- if (!polaris10_is_smc_ram_running(smumgr)) {
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- return -1;
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- }
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-
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- SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
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-
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- cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
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-
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- return polaris10_send_msg_to_smc(smumgr, msg);
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-}
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-
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-
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-/**
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-* Send a message to the SMC with parameter, do not wait for response
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-*
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-* @param smumgr: the address of the powerplay hardware manager.
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-* @param msg: the message to send.
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-* @param parameter: the parameter to send
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-* @return The response that came from the SMC.
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-*/
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-int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
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-{
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- cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
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-
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- return polaris10_send_msg_to_smc_without_waiting(smumgr, msg);
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-}
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-
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-int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
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-{
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- cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
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-
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- cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
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-
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- SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
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-
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- if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
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- printk("Failed to send Message.\n");
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-
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- return 0;
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-}
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-
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-/**
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-* Wait until the SMC is doing nithing. Doing nothing means that the SMC is either turned off or it is sitting on the STOP instruction.
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-*
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-* @param smumgr the address of the powerplay hardware manager.
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-* @param msg the message to send.
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-* @return The response that came from the SMC.
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-*/
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-int polaris10_wait_for_smc_inactive(struct pp_smumgr *smumgr)
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-{
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- /* If the SMC is not even on it qualifies as inactive. */
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- if (!polaris10_is_smc_ram_running(smumgr))
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- return -1;
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-
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- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
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- return 0;
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-}
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-
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-
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-/**
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-* Upload the SMC firmware to the SMC microcontroller.
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-*
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-* @param smumgr the address of the powerplay hardware manager.
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-* @param pFirmware the data structure containing the various sections of the firmware.
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-*/
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-static int polaris10_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
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-{
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- uint32_t byte_count = length;
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-
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- PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -1);
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-
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- cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
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- SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
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-
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- for (; byte_count >= 4; byte_count -= 4)
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- cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
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-
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- SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
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-
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- PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -1);
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-
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- return 0;
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-}
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-
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-static enum cgs_ucode_id polaris10_convert_fw_type_to_cgs(uint32_t fw_type)
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-{
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- enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
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-
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- switch (fw_type) {
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- case UCODE_ID_SMU:
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- result = CGS_UCODE_ID_SMU;
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- break;
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- case UCODE_ID_SMU_SK:
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- result = CGS_UCODE_ID_SMU_SK;
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- break;
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- case UCODE_ID_SDMA0:
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- result = CGS_UCODE_ID_SDMA0;
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- break;
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- case UCODE_ID_SDMA1:
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- result = CGS_UCODE_ID_SDMA1;
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- break;
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- case UCODE_ID_CP_CE:
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- result = CGS_UCODE_ID_CP_CE;
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- break;
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- case UCODE_ID_CP_PFP:
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- result = CGS_UCODE_ID_CP_PFP;
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- break;
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- case UCODE_ID_CP_ME:
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- result = CGS_UCODE_ID_CP_ME;
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- break;
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- case UCODE_ID_CP_MEC:
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- result = CGS_UCODE_ID_CP_MEC;
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- break;
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- case UCODE_ID_CP_MEC_JT1:
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- result = CGS_UCODE_ID_CP_MEC_JT1;
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- break;
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- case UCODE_ID_CP_MEC_JT2:
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- result = CGS_UCODE_ID_CP_MEC_JT2;
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- break;
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- case UCODE_ID_RLC_G:
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- result = CGS_UCODE_ID_RLC_G;
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- break;
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- default:
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- break;
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- }
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-
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- return result;
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-}
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-
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-static int polaris10_upload_smu_firmware_image(struct pp_smumgr *smumgr)
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-{
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- int result = 0;
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- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
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-
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- struct cgs_firmware_info info = {0};
|
|
|
-
|
|
|
- if (smu_data->security_hard_key == 1)
|
|
|
- cgs_get_firmware_info(smumgr->device,
|
|
|
- polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
|
|
|
- else
|
|
|
- cgs_get_firmware_info(smumgr->device,
|
|
|
- polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
|
|
|
-
|
|
|
- /* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/
|
|
|
- result = polaris10_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, POLARIS10_SMC_SIZE);
|
|
|
-
|
|
|
- return result;
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
-* Read a 32bit value from the SMC SRAM space.
|
|
|
-* ALL PARAMETERS ARE IN HOST BYTE ORDER.
|
|
|
-* @param smumgr the address of the powerplay hardware manager.
|
|
|
-* @param smcAddress the address in the SMC RAM to access.
|
|
|
-* @param value and output parameter for the data read from the SMC SRAM.
|
|
|
-*/
|
|
|
-int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
|
|
|
-{
|
|
|
- int result;
|
|
|
-
|
|
|
- result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
|
|
|
-
|
|
|
- if (result)
|
|
|
- return result;
|
|
|
-
|
|
|
- *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
-* Write a 32bit value to the SMC SRAM space.
|
|
|
-* ALL PARAMETERS ARE IN HOST BYTE ORDER.
|
|
|
-* @param smumgr the address of the powerplay hardware manager.
|
|
|
-* @param smc_addr the address in the SMC RAM to access.
|
|
|
-* @param value to write to the SMC SRAM.
|
|
|
-*/
|
|
|
-int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
|
|
|
-{
|
|
|
- int result;
|
|
|
-
|
|
|
- result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
|
|
|
-
|
|
|
- if (result)
|
|
|
- return result;
|
|
|
-
|
|
|
- cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-
|
|
|
-int polaris10_smu_fini(struct pp_smumgr *smumgr)
|
|
|
-{
|
|
|
- if (smumgr->backend) {
|
|
|
- kfree(smumgr->backend);
|
|
|
- smumgr->backend = NULL;
|
|
|
- }
|
|
|
- cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
|
|
|
-static uint32_t polaris10_get_mask_for_firmware_type(uint32_t fw_type)
|
|
|
-{
|
|
|
- uint32_t result = 0;
|
|
|
-
|
|
|
- switch (fw_type) {
|
|
|
- case UCODE_ID_SDMA0:
|
|
|
- result = UCODE_ID_SDMA0_MASK;
|
|
|
- break;
|
|
|
- case UCODE_ID_SDMA1:
|
|
|
- result = UCODE_ID_SDMA1_MASK;
|
|
|
- break;
|
|
|
- case UCODE_ID_CP_CE:
|
|
|
- result = UCODE_ID_CP_CE_MASK;
|
|
|
- break;
|
|
|
- case UCODE_ID_CP_PFP:
|
|
|
- result = UCODE_ID_CP_PFP_MASK;
|
|
|
- break;
|
|
|
- case UCODE_ID_CP_ME:
|
|
|
- result = UCODE_ID_CP_ME_MASK;
|
|
|
- break;
|
|
|
- case UCODE_ID_CP_MEC_JT1:
|
|
|
- case UCODE_ID_CP_MEC_JT2:
|
|
|
- result = UCODE_ID_CP_MEC_MASK;
|
|
|
- break;
|
|
|
- case UCODE_ID_RLC_G:
|
|
|
- result = UCODE_ID_RLC_G_MASK;
|
|
|
- break;
|
|
|
- default:
|
|
|
- printk("UCode type is out of range! \n");
|
|
|
- result = 0;
|
|
|
- }
|
|
|
-
|
|
|
- return result;
|
|
|
-}
|
|
|
-
|
|
|
-/* Populate one firmware image to the data structure */
|
|
|
-
|
|
|
-static int polaris10_populate_single_firmware_entry(struct pp_smumgr *smumgr,
|
|
|
- uint32_t fw_type,
|
|
|
- struct SMU_Entry *entry)
|
|
|
-{
|
|
|
- int result = 0;
|
|
|
- struct cgs_firmware_info info = {0};
|
|
|
-
|
|
|
- result = cgs_get_firmware_info(smumgr->device,
|
|
|
- polaris10_convert_fw_type_to_cgs(fw_type),
|
|
|
- &info);
|
|
|
-
|
|
|
- if (!result) {
|
|
|
- entry->version = info.version;
|
|
|
- entry->id = (uint16_t)fw_type;
|
|
|
- entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
|
|
|
- entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
|
|
|
- entry->meta_data_addr_high = 0;
|
|
|
- entry->meta_data_addr_low = 0;
|
|
|
- entry->data_size_byte = info.image_size;
|
|
|
- entry->num_register_entries = 0;
|
|
|
- }
|
|
|
-
|
|
|
- if (fw_type == UCODE_ID_RLC_G)
|
|
|
- entry->flags = 1;
|
|
|
- else
|
|
|
- entry->flags = 0;
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-static int polaris10_request_smu_load_fw(struct pp_smumgr *smumgr)
|
|
|
-{
|
|
|
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
|
|
|
- uint32_t fw_to_load;
|
|
|
-
|
|
|
- int result = 0;
|
|
|
- struct SMU_DRAMData_TOC *toc;
|
|
|
-
|
|
|
- if (!smumgr->reload_fw) {
|
|
|
- printk(KERN_INFO "[ powerplay ] skip reloading...\n");
|
|
|
- return 0;
|
|
|
- }
|
|
|
-
|
|
|
- if (smu_data->soft_regs_start)
|
|
|
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
|
|
|
- smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
|
|
|
- 0x0);
|
|
|
-
|
|
|
- polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
|
|
|
- polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
|
|
|
-
|
|
|
- toc = (struct SMU_DRAMData_TOC *)smu_data->header;
|
|
|
- toc->num_entries = 0;
|
|
|
- toc->structure_version = 1;
|
|
|
-
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
|
|
-
|
|
|
- polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
|
|
|
- polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
|
|
|
-
|
|
|
- fw_to_load = UCODE_ID_RLC_G_MASK
|
|
|
- + UCODE_ID_SDMA0_MASK
|
|
|
- + UCODE_ID_SDMA1_MASK
|
|
|
- + UCODE_ID_CP_CE_MASK
|
|
|
- + UCODE_ID_CP_ME_MASK
|
|
|
- + UCODE_ID_CP_PFP_MASK
|
|
|
- + UCODE_ID_CP_MEC_MASK;
|
|
|
-
|
|
|
- if (polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
|
|
|
- printk(KERN_ERR "Fail to Request SMU Load uCode");
|
|
|
-
|
|
|
- return result;
|
|
|
-}
|
|
|
-
|
|
|
-/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
|
|
|
-static int polaris10_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
|
|
|
-{
|
|
|
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
|
|
|
- uint32_t fw_mask = polaris10_get_mask_for_firmware_type(fw_type);
|
|
|
- uint32_t ret;
|
|
|
- /* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
|
|
|
- ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
|
|
|
- smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
|
|
|
- fw_mask, fw_mask);
|
|
|
-
|
|
|
- return ret;
|
|
|
-}
|
|
|
-
|
|
|
-static int polaris10_reload_firmware(struct pp_smumgr *smumgr)
|
|
|
-{
|
|
|
- return smumgr->smumgr_funcs->start_smu(smumgr);
|
|
|
-}
|
|
|
|
|
|
static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
|
|
|
{
|
|
|
@@ -670,7 +101,7 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
|
|
|
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
|
|
|
|
|
|
if (0 != smu_data->avfs.avfs_btc_param) {
|
|
|
- if (0 != polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
|
|
|
+ if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
|
|
|
printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
|
|
|
result = -1;
|
|
|
}
|
|
|
@@ -698,7 +129,7 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
|
|
|
graphics_level_size = sizeof(avfs_graphics_level_polaris10);
|
|
|
u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
|
|
|
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_read_smc_sram_dword(smumgr,
|
|
|
+ PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
|
|
|
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
|
|
|
&dpm_table_start, 0x40000),
|
|
|
"[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
|
|
|
@@ -709,14 +140,14 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
|
|
|
|
|
|
vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
|
|
|
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, vr_config_address,
|
|
|
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_address,
|
|
|
(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
|
|
|
"[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
|
|
|
return -1);
|
|
|
|
|
|
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
|
|
|
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
|
|
|
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
|
|
|
(uint8_t *)(&avfs_graphics_level_polaris10),
|
|
|
graphics_level_size, 0x40000),
|
|
|
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
|
|
|
@@ -724,7 +155,7 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
|
|
|
|
|
|
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
|
|
|
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
|
|
|
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
|
|
|
(uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
|
|
|
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
|
|
|
return -1);
|
|
|
@@ -733,7 +164,7 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
|
|
|
|
|
|
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
|
|
|
|
|
|
- PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
|
|
|
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
|
|
|
(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
|
|
|
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
|
|
|
return -1);
|
|
|
@@ -794,7 +225,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
|
|
|
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
|
|
|
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
|
|
|
|
|
|
- result = polaris10_upload_smu_firmware_image(smumgr);
|
|
|
+ result = smu7_upload_smu_firmware_image(smumgr);
|
|
|
if (result != 0)
|
|
|
return result;
|
|
|
|
|
|
@@ -813,7 +244,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
|
|
|
|
|
|
|
|
|
/* Call Test SMU message with 0x20000 offset to trigger SMU start */
|
|
|
- polaris10_send_msg_to_smc_offset(smumgr);
|
|
|
+ smu7_send_msg_to_smc_offset(smumgr);
|
|
|
|
|
|
/* Wait done bit to be set */
|
|
|
/* Check pass/failed indicator */
|
|
|
@@ -854,12 +285,12 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
|
|
|
SMC_SYSCON_RESET_CNTL,
|
|
|
rst_reg, 1);
|
|
|
|
|
|
- result = polaris10_upload_smu_firmware_image(smumgr);
|
|
|
+ result = smu7_upload_smu_firmware_image(smumgr);
|
|
|
if (result != 0)
|
|
|
return result;
|
|
|
|
|
|
/* Set smc instruct start point at 0x0 */
|
|
|
- polaris10_program_jump_on_start(smumgr);
|
|
|
+ smu7_program_jump_on_start(smumgr);
|
|
|
|
|
|
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
|
|
|
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
|
|
|
@@ -882,10 +313,10 @@ static int polaris10_start_smu(struct pp_smumgr *smumgr)
|
|
|
bool SMU_VFT_INTACT;
|
|
|
|
|
|
/* Only start SMC if SMC RAM is not running */
|
|
|
- if (!polaris10_is_smc_ram_running(smumgr)) {
|
|
|
+ if (!smu7_is_smc_ram_running(smumgr)) {
|
|
|
SMU_VFT_INTACT = false;
|
|
|
smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
|
|
|
- smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
|
|
|
+ smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
|
|
|
|
|
|
/* Check if SMU is running in protected mode */
|
|
|
if (smu_data->protected_mode == 0) {
|
|
|
@@ -895,7 +326,7 @@ static int polaris10_start_smu(struct pp_smumgr *smumgr)
|
|
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/* If failed, try with different security Key. */
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if (result != 0) {
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- smu_data->security_hard_key ^= 1;
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+ smu_data->smu7_data.security_hard_key ^= 1;
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result = polaris10_start_smu_in_protection_mode(smumgr);
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}
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}
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@@ -907,71 +338,35 @@ static int polaris10_start_smu(struct pp_smumgr *smumgr)
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} else
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SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
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- smu_data->post_initial_boot = true;
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polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
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/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
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- polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
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- &(smu_data->soft_regs_start), 0x40000);
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+ smu7_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
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+ &(smu_data->smu7_data.soft_regs_start), 0x40000);
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- result = polaris10_request_smu_load_fw(smumgr);
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+ result = smu7_request_smu_load_fw(smumgr);
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return result;
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}
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+static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
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+{
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+ uint32_t efuse;
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+
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+ efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
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+ efuse &= 0x00000001;
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+ if (efuse)
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+ return true;
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+
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+ return false;
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+}
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+
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static int polaris10_smu_init(struct pp_smumgr *smumgr)
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{
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- struct polaris10_smumgr *smu_data;
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- uint8_t *internal_buf;
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- uint64_t mc_addr = 0;
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+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
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int i;
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- /* Allocate memory for backend private data */
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- smu_data = (struct polaris10_smumgr *)(smumgr->backend);
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- smu_data->header_buffer.data_size =
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- ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
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- smu_data->smu_buffer.data_size = 200*4096;
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- smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
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-/* Allocate FW image data structure and header buffer and
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- * send the header buffer address to SMU */
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- smu_allocate_memory(smumgr->device,
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|
- smu_data->header_buffer.data_size,
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|
- CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
|
|
|
- PAGE_SIZE,
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|
- &mc_addr,
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|
|
- &smu_data->header_buffer.kaddr,
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|
|
- &smu_data->header_buffer.handle);
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|
-
|
|
|
- smu_data->header = smu_data->header_buffer.kaddr;
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|
|
- smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
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|
- smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
|
|
|
-
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|
- PP_ASSERT_WITH_CODE((NULL != smu_data->header),
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|
|
- "Out of memory.",
|
|
|
- kfree(smumgr->backend);
|
|
|
- cgs_free_gpu_mem(smumgr->device,
|
|
|
- (cgs_handle_t)smu_data->header_buffer.handle);
|
|
|
- return -1);
|
|
|
-
|
|
|
-/* Allocate buffer for SMU internal buffer and send the address to SMU.
|
|
|
- * Iceland SMU does not need internal buffer.*/
|
|
|
- smu_allocate_memory(smumgr->device,
|
|
|
- smu_data->smu_buffer.data_size,
|
|
|
- CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
|
|
|
- PAGE_SIZE,
|
|
|
- &mc_addr,
|
|
|
- &smu_data->smu_buffer.kaddr,
|
|
|
- &smu_data->smu_buffer.handle);
|
|
|
-
|
|
|
- internal_buf = smu_data->smu_buffer.kaddr;
|
|
|
- smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
|
|
|
- smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
|
|
|
-
|
|
|
- PP_ASSERT_WITH_CODE((NULL != internal_buf),
|
|
|
- "Out of memory.",
|
|
|
- kfree(smumgr->backend);
|
|
|
- cgs_free_gpu_mem(smumgr->device,
|
|
|
- (cgs_handle_t)smu_data->smu_buffer.handle);
|
|
|
- return -1;);
|
|
|
+ if (smu7_init(smumgr))
|
|
|
+ return -EINVAL;
|
|
|
|
|
|
if (polaris10_is_hw_avfs_present(smumgr))
|
|
|
smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
|
|
|
@@ -986,13 +381,13 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr)
|
|
|
|
|
|
static const struct pp_smumgr_func polaris10_smu_funcs = {
|
|
|
.smu_init = polaris10_smu_init,
|
|
|
- .smu_fini = polaris10_smu_fini,
|
|
|
+ .smu_fini = smu7_smu_fini,
|
|
|
.start_smu = polaris10_start_smu,
|
|
|
- .check_fw_load_finish = polaris10_check_fw_load_finish,
|
|
|
- .request_smu_load_fw = polaris10_reload_firmware,
|
|
|
+ .check_fw_load_finish = smu7_check_fw_load_finish,
|
|
|
+ .request_smu_load_fw = smu7_reload_firmware,
|
|
|
.request_smu_load_specific_fw = NULL,
|
|
|
- .send_msg_to_smc = polaris10_send_msg_to_smc,
|
|
|
- .send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter,
|
|
|
+ .send_msg_to_smc = smu7_send_msg_to_smc,
|
|
|
+ .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
|
|
|
.download_pptable_settings = NULL,
|
|
|
.upload_pptable_settings = NULL,
|
|
|
.update_smc_table = polaris10_update_smc_table,
|
|
|
@@ -1015,7 +410,7 @@ int polaris10_smum_init(struct pp_smumgr *smumgr)
|
|
|
polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
|
|
|
|
|
|
if (polaris10_smu == NULL)
|
|
|
- return -1;
|
|
|
+ return -EINVAL;
|
|
|
|
|
|
smumgr->backend = polaris10_smu;
|
|
|
smumgr->smumgr_funcs = &polaris10_smu_funcs;
|
Rex Zhu