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@@ -183,7 +183,6 @@ ENTRY(sie64a)
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xc __SF_EMPTY+16(16,%r15),__SF_EMPTY+16(%r15) # host id & reason
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tm __LC_CPU_FLAGS+7,_CIF_FPU # load guest fp/vx registers ?
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jno .Lsie_load_guest_gprs
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- lg %r12,__LC_THREAD_INFO # load fp/vx regs save area
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brasl %r14,load_fpu_regs # load guest fp/vx regs
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.Lsie_load_guest_gprs:
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lmg %r0,%r13,0(%r3) # load guest gprs 0-13
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@@ -752,14 +751,16 @@ ENTRY(psw_idle)
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* of the register contents at system call or io return.
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*/
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ENTRY(save_fpu_regs)
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+ lg %r2,__LC_CURRENT
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+ aghi %r2,__TASK_thread
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tm __LC_CPU_FLAGS+7,_CIF_FPU
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bor %r14
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- stfpc __FPU_fpc(%r2)
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+ stfpc __THREAD_FPU_fpc(%r2)
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.Lsave_fpu_regs_fpc_end:
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- lg %r3,__FPU_regs(%r2)
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+ lg %r3,__THREAD_FPU_regs(%r2)
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ltgr %r3,%r3
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jz .Lsave_fpu_regs_done # no save area -> set CIF_FPU
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- tm __FPU_flags+3(%r2),FPU_USE_VX
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+ tm __THREAD_FPU_flags+3(%r2),FPU_USE_VX
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jz .Lsave_fpu_regs_fp # no -> store FP regs
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.Lsave_fpu_regs_vx_low:
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VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
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@@ -794,20 +795,19 @@ ENTRY(save_fpu_regs)
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* FP/VX state, the vector-enablement control, CR0.46, is either set or cleared.
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*
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* There are special calling conventions to fit into sysc and io return work:
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- * %r12: __LC_THREAD_INFO
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* %r15: <kernel stack>
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* The function requires:
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* %r4 and __SF_EMPTY+32(%r15)
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*/
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load_fpu_regs:
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+ lg %r4,__LC_CURRENT
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+ aghi %r4,__TASK_thread
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tm __LC_CPU_FLAGS+7,_CIF_FPU
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bnor %r14
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- lg %r4,__TI_task(%r12)
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- la %r4,__THREAD_fpu(%r4)
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- lfpc __FPU_fpc(%r4)
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+ lfpc __THREAD_FPU_fpc(%r4)
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stctg %c0,%c0,__SF_EMPTY+32(%r15) # store CR0
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- tm __FPU_flags+3(%r4),FPU_USE_VX # VX-enabled task ?
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- lg %r4,__FPU_regs(%r4) # %r4 <- reg save area
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+ tm __THREAD_FPU_flags+3(%r4),FPU_USE_VX # VX-enabled task ?
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+ lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
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jz .Lload_fpu_regs_fp_ctl # -> no VX, load FP regs
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.Lload_fpu_regs_vx_ctl:
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tm __SF_EMPTY+32+5(%r15),2 # test VX control
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@@ -1190,13 +1190,14 @@ cleanup_critical:
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jhe 2f
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clg %r9,BASED(.Lcleanup_save_fpu_fpc_end)
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jhe 1f
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+ lg %r2,__LC_CURRENT
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0: # Store floating-point controls
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- stfpc __FPU_fpc(%r2)
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+ stfpc __THREAD_FPU_fpc(%r2)
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1: # Load register save area and check if VX is active
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- lg %r3,__FPU_regs(%r2)
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+ lg %r3,__THREAD_FPU_regs(%r2)
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ltgr %r3,%r3
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jz 5f # no save area -> set CIF_FPU
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- tm __FPU_flags+3(%r2),FPU_USE_VX
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+ tm __THREAD_FPU_flags+3(%r2),FPU_USE_VX
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jz 4f # no VX -> store FP regs
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2: # Store vector registers (V0-V15)
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VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
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@@ -1250,11 +1251,10 @@ cleanup_critical:
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jhe 5f
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clg %r9,BASED(.Lcleanup_load_fpu_regs_vx_ctl)
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jhe 6f
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- lg %r4,__TI_task(%r12)
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- la %r4,__THREAD_fpu(%r4)
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- lfpc __FPU_fpc(%r4)
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- tm __FPU_flags+3(%r4),FPU_USE_VX # VX-enabled task ?
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- lg %r4,__FPU_regs(%r4) # %r4 <- reg save area
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+ lg %r4,__LC_CURRENT
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+ lfpc __THREAD_FPU_fpc(%r4)
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+ tm __THREAD_FPU_flags+3(%r4),FPU_USE_VX # VX-enabled task ?
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+ lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
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jz 3f # -> no VX, load FP regs
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6: # Set VX-enablement control
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stctg %c0,%c0,__SF_EMPTY+32(%r15) # store CR0
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