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@@ -817,6 +817,85 @@
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status = "disabled";
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};
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+
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+ dss: dss@58000000 {
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+ compatible = "ti,omap4-dss";
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+ reg = <0x58000000 0x80>;
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+ status = "disabled";
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+ ti,hwmods = "dss_core";
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+ clocks = <&dss_dss_clk>;
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+ clock-names = "fck";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ dispc@58001000 {
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+ compatible = "ti,omap4-dispc";
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+ reg = <0x58001000 0x1000>;
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+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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+ ti,hwmods = "dss_dispc";
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+ clocks = <&dss_dss_clk>;
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+ clock-names = "fck";
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+ };
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+
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+ rfbi: encoder@58002000 {
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+ compatible = "ti,omap4-rfbi";
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+ reg = <0x58002000 0x1000>;
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+ status = "disabled";
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+ ti,hwmods = "dss_rfbi";
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+ clocks = <&dss_dss_clk>, <&dss_fck>;
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+ clock-names = "fck", "ick";
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+ };
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+
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+ venc: encoder@58003000 {
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+ compatible = "ti,omap4-venc";
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+ reg = <0x58003000 0x1000>;
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+ status = "disabled";
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+ ti,hwmods = "dss_venc";
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+ clocks = <&dss_tv_clk>;
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+ clock-names = "fck";
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+ };
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+
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+ dsi1: encoder@58004000 {
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+ compatible = "ti,omap4-dsi";
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+ reg = <0x58004000 0x200>,
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+ <0x58004200 0x40>,
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+ <0x58004300 0x20>;
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+ reg-names = "proto", "phy", "pll";
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+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ ti,hwmods = "dss_dsi1";
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+ clocks = <&dss_dss_clk>, <&dss_sys_clk>;
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+ clock-names = "fck", "sys_clk";
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+ };
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+
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+ dsi2: encoder@58005000 {
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+ compatible = "ti,omap4-dsi";
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+ reg = <0x58005000 0x200>,
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+ <0x58005200 0x40>,
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+ <0x58005300 0x20>;
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+ reg-names = "proto", "phy", "pll";
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+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ ti,hwmods = "dss_dsi2";
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+ clocks = <&dss_dss_clk>, <&dss_sys_clk>;
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+ clock-names = "fck", "sys_clk";
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+ };
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+
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+ hdmi: encoder@58006000 {
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+ compatible = "ti,omap4-hdmi";
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+ reg = <0x58006000 0x200>,
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+ <0x58006200 0x100>,
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+ <0x58006300 0x100>,
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+ <0x58006400 0x1000>;
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+ reg-names = "wp", "pll", "phy", "core";
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+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ ti,hwmods = "dss_hdmi";
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+ clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
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+ clock-names = "fck", "sys_clk";
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+ };
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+ };
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};
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};
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