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@@ -78,6 +78,9 @@
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#define CFG_MEM_RAM_SHUTDOWN 0x00000070
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#define BLOCK_MEM_RDY 0x00000074
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+/* Max retry for link down */
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+#define MAX_LINK_DOWN_RETRY 3
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+
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struct xgene_ahci_context {
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struct ahci_host_priv *hpriv;
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struct device *dev;
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@@ -145,6 +148,14 @@ static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
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return rc;
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}
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+static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
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+{
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+ void __iomem *diagcsr = ctx->csr_diag;
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+
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+ return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&
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+ readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);
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+}
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+
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/**
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* xgene_ahci_read_id - Read ID data from the specified device
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* @dev: device
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@@ -229,8 +240,11 @@ static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
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* and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
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* report disparity error and etc. In addition, during COMRESET, there can
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* be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
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- * SERR_10B_8B_ERR, the PHY receiver line must be reseted. The following
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- * algorithm is followed to proper configure the hardware PHY during COMRESET:
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+ * SERR_10B_8B_ERR, the PHY receiver line must be reseted. Also during long
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+ * reboot cycle regression, sometimes the PHY reports link down even if the
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+ * device is present because of speed negotiation failure. so need to retry
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+ * the COMRESET to get the link up. The following algorithm is followed to
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+ * proper configure the hardware PHY during COMRESET:
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*
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* Alg Part 1:
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* 1. Start the PHY at Gen3 speed (default setting)
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@@ -246,9 +260,15 @@ static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
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* Alg Part 2:
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* 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
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* reported in the register PORT_SCR_ERR, then reset the PHY receiver line
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- * 2. Go to Alg Part 3
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+ * 2. Go to Alg Part 4
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*
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* Alg Part 3:
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+ * 1. Check the PORT_SCR_STAT to see whether device presence detected but PHY
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+ * communication establishment failed and maximum link down attempts are
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+ * less than Max attempts 3 then goto Alg Part 1.
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+ * 2. Go to Alg Part 4.
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+ *
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+ * Alg Part 4:
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* 1. Clear any pending from register PORT_SCR_ERR.
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*
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* NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
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@@ -267,19 +287,27 @@ static int xgene_ahci_do_hardreset(struct ata_link *link,
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u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
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void __iomem *port_mmio = ahci_port_base(ap);
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struct ata_taskfile tf;
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+ int link_down_retry = 0;
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int rc;
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- u32 val;
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-
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- /* clear D2H reception area to properly wait for D2H FIS */
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- ata_tf_init(link->device, &tf);
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- tf.command = ATA_BUSY;
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- ata_tf_to_fis(&tf, 0, 0, d2h_fis);
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- rc = sata_link_hardreset(link, timing, deadline, online,
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+ u32 val, sstatus;
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+
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+ do {
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+ /* clear D2H reception area to properly wait for D2H FIS */
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+ ata_tf_init(link->device, &tf);
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+ tf.command = ATA_BUSY;
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+ ata_tf_to_fis(&tf, 0, 0, d2h_fis);
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+ rc = sata_link_hardreset(link, timing, deadline, online,
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ahci_check_ready);
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+ if (*online) {
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+ val = readl(port_mmio + PORT_SCR_ERR);
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+ if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
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+ dev_warn(ctx->dev, "link has error\n");
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+ break;
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+ }
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- val = readl(port_mmio + PORT_SCR_ERR);
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- if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
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- dev_warn(ctx->dev, "link has error\n");
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+ sata_scr_read(link, SCR_STATUS, &sstatus);
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+ } while (link_down_retry++ < MAX_LINK_DOWN_RETRY &&
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+ (sstatus & 0xff) == 0x1);
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/* clear all errors if any pending */
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val = readl(port_mmio + PORT_SCR_ERR);
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@@ -467,6 +495,11 @@ static int xgene_ahci_probe(struct platform_device *pdev)
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return -ENODEV;
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}
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+ if (xgene_ahci_is_memram_inited(ctx)) {
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+ dev_info(dev, "skip clock and PHY initialization\n");
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+ goto skip_clk_phy;
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+ }
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+
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/* Due to errata, HW requires full toggle transition */
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rc = ahci_platform_enable_clks(hpriv);
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if (rc)
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@@ -479,7 +512,7 @@ static int xgene_ahci_probe(struct platform_device *pdev)
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/* Configure the host controller */
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xgene_ahci_hw_init(hpriv);
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-
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+skip_clk_phy:
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hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ;
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rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info);
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Linus Torvalds