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@@ -422,9 +422,9 @@ void pciehp_set_attention_status(struct slot *slot, u8 value)
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default:
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return;
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}
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+ pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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- pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
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}
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void pciehp_green_led_on(struct slot *slot)
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@@ -602,6 +602,8 @@ void pcie_enable_notification(struct controller *ctrl)
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PCI_EXP_SLTCTL_DLLSCE);
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pcie_write_cmd(ctrl, cmd, mask);
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+ ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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+ pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
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}
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static void pcie_disable_notification(struct controller *ctrl)
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@@ -613,6 +615,8 @@ static void pcie_disable_notification(struct controller *ctrl)
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PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
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PCI_EXP_SLTCTL_DLLSCE);
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pcie_write_cmd(ctrl, 0, mask);
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+ ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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+ pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
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}
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/*
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@@ -640,6 +644,8 @@ int pciehp_reset_slot(struct slot *slot, int probe)
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stat_mask |= PCI_EXP_SLTSTA_DLLSC;
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pcie_write_cmd(ctrl, 0, ctrl_mask);
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+ ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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+ pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
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if (pciehp_poll_mode)
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del_timer_sync(&ctrl->poll_timer);
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@@ -647,6 +653,8 @@ int pciehp_reset_slot(struct slot *slot, int probe)
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pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
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pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
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+ ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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+ pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
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if (pciehp_poll_mode)
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int_poll_timeout(ctrl->poll_timer.data);
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