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ARM: davinci: DA8xx+DMx combined kernels need PATCH_PHYS_VIRT

We already forbid that combination when AUTO_ZRELADDR is disabled,
for the same reason that the two have their RAM at different
physical addresses as seen from the CPU.

This does the same change for PATCH_PHYS_VIRT: if you disable
either of the options, Kconfig now enforces that you have to
pick one or the other SoC family.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Arnd Bergmann 9 years ago
parent
a32b4fe90a
commit
ce32c5c5a3
2 changed files with 3 additions and 4 deletions
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  1. 1 0
      arch/arm/Kconfig
  2. 2 4
      arch/arm/mach-davinci/Kconfig

+ 1 - 0
arch/arm/Kconfig
View File 

@@ -623,6 +623,7 @@ config ARCH_DAVINCI
 
 	select ARCH_HAS_HOLES_MEMORYMODEL
 
 	select ARCH_REQUIRE_GPIOLIB
 
 	select CLKDEV_LOOKUP
 
+	select CPU_ARM926T
 
 	select GENERIC_ALLOCATOR
 
 	select GENERIC_CLOCKEVENTS
 
 	select GENERIC_IRQ_CHIP

+ 2 - 4
arch/arm/mach-davinci/Kconfig
View File 

@@ -9,7 +9,6 @@ config CP_INTC
 
 
 config ARCH_DAVINCI_DMx
 
 	bool
 
-	select CPU_ARM926T
 
 
 menu "TI DaVinci Implementations"
 
 
@@ -32,7 +31,7 @@ config ARCH_DAVINCI_DM646x
 
 
 config ARCH_DAVINCI_DA830
 
 	bool "DA830/OMAP-L137/AM17x based system"
 
-	depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR
 
+	depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
 
 	select ARCH_DAVINCI_DA8XX
 
 	# needed on silicon revs 1.0, 1.1:
 
 	select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE
 
@@ -40,13 +39,12 @@ config ARCH_DAVINCI_DA830
 
 
 config ARCH_DAVINCI_DA850
 
 	bool "DA850/OMAP-L138/AM18x based system"
 
-	depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR
 
+	depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
 
 	select ARCH_DAVINCI_DA8XX
 
 	select CP_INTC
 
 
 config ARCH_DAVINCI_DA8XX
 
 	bool
 
-	select CPU_ARM926T
 
 
 config ARCH_DAVINCI_DM365
 
 	bool "DaVinci 365 based system"