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@@ -32,23 +32,13 @@
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* r2,r3 = Hypervisor pgd pointer
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*
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* The init scenario is:
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- * - We jump in HYP with four parameters: boot HYP pgd, runtime HYP pgd,
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- * runtime stack, runtime vectors
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- * - Enable the MMU with the boot pgd
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- * - Jump to a target into the trampoline page (remember, this is the same
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- * physical page!)
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- * - Now switch to the runtime pgd (same VA, and still the same physical
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- * page!)
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+ * - We jump in HYP with 3 parameters: runtime HYP pgd, runtime stack,
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+ * runtime vectors
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* - Invalidate TLBs
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* - Set stack and vectors
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+ * - Setup the page tables
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+ * - Enable the MMU
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* - Profit! (or eret, if you only care about the code).
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- *
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- * As we only have four registers available to pass parameters (and we
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- * need six), we split the init in two phases:
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- * - Phase 1: r0 = 0, r1 = 0, r2,r3 contain the boot PGD.
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- * Provides the basic HYP init, and enable the MMU.
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- * - Phase 2: r0 = ToS, r1 = vectors, r2,r3 contain the runtime PGD.
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- * Switches to the runtime PGD, set stack and vectors.
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*/
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.text
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@@ -68,8 +58,11 @@ __kvm_hyp_init:
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W(b) .
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__do_hyp_init:
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- cmp r0, #0 @ We have a SP?
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- bne phase2 @ Yes, second stage init
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+ @ Set stack pointer
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+ mov sp, r0
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+
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+ @ Set HVBAR to point to the HYP vectors
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+ mcr p15, 4, r1, c12, c0, 0 @ HVBAR
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@ Set the HTTBR to point to the hypervisor PGD pointer passed
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mcrr p15, 4, rr_lo_hi(r2, r3), c2
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@@ -114,33 +107,9 @@ __do_hyp_init:
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THUMB( ldr r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE) )
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orr r1, r1, r2
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orr r0, r0, r1
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- isb
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mcr p15, 4, r0, c1, c0, 0 @ HSCR
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-
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- @ End of init phase-1
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- eret
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-
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-phase2:
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- @ Set stack pointer
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- mov sp, r0
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-
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- @ Set HVBAR to point to the HYP vectors
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- mcr p15, 4, r1, c12, c0, 0 @ HVBAR
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-
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- @ Jump to the trampoline page
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- ldr r0, =TRAMPOLINE_VA
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- adr r1, target
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- bfi r0, r1, #0, #PAGE_SHIFT
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- ret r0
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-
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-target: @ We're now in the trampoline code, switch page tables
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- mcrr p15, 4, rr_lo_hi(r2, r3), c2
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isb
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- @ Invalidate the old TLBs
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- mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
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- dsb ish
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-
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eret
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.ltorg
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