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@@ -240,6 +240,46 @@ i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
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return ret_code;
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}
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+/**
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+ * i40e_write_nvm_aq - Writes Shadow RAM.
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+ * @hw: pointer to the HW structure.
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+ * @module_pointer: module pointer location in words from the NVM beginning
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+ * @offset: offset in words from module start
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+ * @words: number of words to write
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+ * @data: buffer with words to write to the Shadow RAM
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+ * @last_command: tells the AdminQ that this is the last command
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+ *
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+ * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
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+ **/
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+i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
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+ u32 offset, u16 words, void *data,
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+ bool last_command)
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+{
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+ i40e_status ret_code = I40E_ERR_NVM;
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+
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+ /* Here we are checking the SR limit only for the flat memory model.
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+ * We cannot do it for the module-based model, as we did not acquire
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+ * the NVM resource yet (we cannot get the module pointer value).
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+ * Firmware will check the module-based model.
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+ */
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+ if ((offset + words) > hw->nvm.sr_size)
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+ hw_dbg(hw, "NVM write error: offset beyond Shadow RAM limit.\n");
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+ else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
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+ /* We can write only up to 4KB (one sector), in one AQ write */
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+ hw_dbg(hw, "NVM write fail error: cannot write more than 4KB in a single write.\n");
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+ else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
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+ != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
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+ /* A single write cannot spread over two sectors */
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+ hw_dbg(hw, "NVM write error: cannot spread over two sectors in a single write.\n");
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+ else
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+ ret_code = i40e_aq_update_nvm(hw, module_pointer,
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+ 2 * offset, /*bytes*/
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+ 2 * words, /*bytes*/
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+ data, last_command, NULL);
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+
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+ return ret_code;
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+}
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+
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/**
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* i40e_calc_nvm_checksum - Calculates and returns the checksum
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* @hw: pointer to hardware structure
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@@ -309,6 +349,27 @@ i40e_calc_nvm_checksum_exit:
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return ret_code;
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}
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+/**
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+ * i40e_update_nvm_checksum - Updates the NVM checksum
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+ * @hw: pointer to hardware structure
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+ *
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+ * NVM ownership must be acquired before calling this function and released
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+ * on ARQ completion event reception by caller.
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+ * This function will commit SR to NVM.
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+ **/
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+i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw)
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+{
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+ i40e_status ret_code = 0;
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+ u16 checksum;
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+
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+ ret_code = i40e_calc_nvm_checksum(hw, &checksum);
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+ if (!ret_code)
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+ ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
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+ 1, &checksum, true);
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+
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+ return ret_code;
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+}
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+
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/**
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* i40e_validate_nvm_checksum - Validate EEPROM checksum
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* @hw: pointer to hardware structure
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@@ -346,3 +407,453 @@ i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
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i40e_validate_nvm_checksum_exit:
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return ret_code;
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}
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+
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+static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ u8 *bytes, int *errno);
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+static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ u8 *bytes, int *errno);
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+static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ u8 *bytes, int *errno);
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+static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ int *errno);
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+static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ int *errno);
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+static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ u8 *bytes, int *errno);
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+static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ u8 *bytes, int *errno);
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+static inline u8 i40e_nvmupd_get_module(u32 val)
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+{
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+ return (u8)(val & I40E_NVM_MOD_PNT_MASK);
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+}
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+static inline u8 i40e_nvmupd_get_transaction(u32 val)
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+{
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+ return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
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+}
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+
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+/**
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+ * i40e_nvmupd_command - Process an NVM update command
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+ * @hw: pointer to hardware structure
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+ * @cmd: pointer to nvm update command
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+ * @bytes: pointer to the data buffer
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+ * @errno: pointer to return error code
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+ *
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+ * Dispatches command depending on what update state is current
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+ **/
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+i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ u8 *bytes, int *errno)
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+{
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+ i40e_status status;
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+
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+ /* assume success */
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+ *errno = 0;
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+
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+ switch (hw->nvmupd_state) {
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+ case I40E_NVMUPD_STATE_INIT:
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+ status = i40e_nvmupd_state_init(hw, cmd, bytes, errno);
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+ break;
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+
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+ case I40E_NVMUPD_STATE_READING:
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+ status = i40e_nvmupd_state_reading(hw, cmd, bytes, errno);
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+ break;
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+
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+ case I40E_NVMUPD_STATE_WRITING:
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+ status = i40e_nvmupd_state_writing(hw, cmd, bytes, errno);
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+ break;
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+
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+ default:
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+ /* invalid state, should never happen */
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+ status = I40E_NOT_SUPPORTED;
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+ *errno = -ESRCH;
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+ break;
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+ }
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+ return status;
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+}
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+
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+/**
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+ * i40e_nvmupd_state_init - Handle NVM update state Init
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+ * @hw: pointer to hardware structure
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+ * @cmd: pointer to nvm update command buffer
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+ * @bytes: pointer to the data buffer
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+ * @errno: pointer to return error code
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+ *
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+ * Process legitimate commands of the Init state and conditionally set next
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+ * state. Reject all other commands.
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+ **/
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+static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ u8 *bytes, int *errno)
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+{
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+ i40e_status status = 0;
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+ enum i40e_nvmupd_cmd upd_cmd;
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+
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+ upd_cmd = i40e_nvmupd_validate_command(hw, cmd, errno);
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+
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+ switch (upd_cmd) {
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+ case I40E_NVMUPD_READ_SA:
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+ status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
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+ if (status) {
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+ *errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
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+ } else {
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+ status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno);
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+ i40e_release_nvm(hw);
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+ }
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+ break;
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+
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+ case I40E_NVMUPD_READ_SNT:
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+ status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
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+ if (status) {
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+ *errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
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+ } else {
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+ status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno);
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+ hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
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+ }
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+ break;
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+
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+ case I40E_NVMUPD_WRITE_ERA:
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+ status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
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+ if (status) {
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+ *errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
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+ } else {
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+ status = i40e_nvmupd_nvm_erase(hw, cmd, errno);
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+ if (status)
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+ i40e_release_nvm(hw);
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+ else
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+ hw->aq.nvm_release_on_done = true;
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+ }
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+ break;
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+
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+ case I40E_NVMUPD_WRITE_SA:
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+ status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
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+ if (status) {
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+ *errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
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+ } else {
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+ status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno);
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+ if (status)
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+ i40e_release_nvm(hw);
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+ else
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+ hw->aq.nvm_release_on_done = true;
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+ }
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+ break;
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+
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+ case I40E_NVMUPD_WRITE_SNT:
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+ status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
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+ if (status) {
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+ *errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
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+ } else {
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+ status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno);
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+ hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
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+ }
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+ break;
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+
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+ case I40E_NVMUPD_CSUM_SA:
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+ status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
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+ if (status) {
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+ *errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
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+ } else {
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+ status = i40e_update_nvm_checksum(hw);
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+ if (status) {
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+ *errno = hw->aq.asq_last_status ?
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+ i40e_aq_rc_to_posix(hw->aq.asq_last_status) :
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+ -EIO;
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+ i40e_release_nvm(hw);
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+ } else {
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+ hw->aq.nvm_release_on_done = true;
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+ }
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+ }
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+ break;
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+
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+ default:
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+ status = I40E_ERR_NVM;
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+ *errno = -ESRCH;
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+ break;
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+ }
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+ return status;
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+}
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+
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+/**
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+ * i40e_nvmupd_state_reading - Handle NVM update state Reading
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+ * @hw: pointer to hardware structure
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+ * @cmd: pointer to nvm update command buffer
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+ * @bytes: pointer to the data buffer
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+ * @errno: pointer to return error code
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+ *
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+ * NVM ownership is already held. Process legitimate commands and set any
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+ * change in state; reject all other commands.
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+ **/
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+static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ u8 *bytes, int *errno)
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+{
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+ i40e_status status;
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+ enum i40e_nvmupd_cmd upd_cmd;
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+
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+ upd_cmd = i40e_nvmupd_validate_command(hw, cmd, errno);
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+
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+ switch (upd_cmd) {
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+ case I40E_NVMUPD_READ_SA:
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+ case I40E_NVMUPD_READ_CON:
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+ status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno);
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+ break;
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+
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+ case I40E_NVMUPD_READ_LCB:
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+ status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno);
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+ i40e_release_nvm(hw);
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+ hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
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+ break;
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+
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+ default:
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+ status = I40E_NOT_SUPPORTED;
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+ *errno = -ESRCH;
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+ break;
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+ }
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+ return status;
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+}
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+
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+/**
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+ * i40e_nvmupd_state_writing - Handle NVM update state Writing
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+ * @hw: pointer to hardware structure
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+ * @cmd: pointer to nvm update command buffer
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+ * @bytes: pointer to the data buffer
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+ * @errno: pointer to return error code
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+ *
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+ * NVM ownership is already held. Process legitimate commands and set any
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+ * change in state; reject all other commands
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+ **/
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+static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ u8 *bytes, int *errno)
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+{
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+ i40e_status status;
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+ enum i40e_nvmupd_cmd upd_cmd;
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+
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+ upd_cmd = i40e_nvmupd_validate_command(hw, cmd, errno);
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+
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+ switch (upd_cmd) {
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+ case I40E_NVMUPD_WRITE_CON:
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+ status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno);
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+ break;
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+
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+ case I40E_NVMUPD_WRITE_LCB:
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+ status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno);
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+ if (!status) {
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+ hw->aq.nvm_release_on_done = true;
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+ hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
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+ }
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+ break;
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+
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+ case I40E_NVMUPD_CSUM_CON:
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+ status = i40e_update_nvm_checksum(hw);
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+ if (status)
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+ *errno = hw->aq.asq_last_status ?
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+ i40e_aq_rc_to_posix(hw->aq.asq_last_status) :
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+ -EIO;
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+ break;
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+
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+ case I40E_NVMUPD_CSUM_LCB:
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+ status = i40e_update_nvm_checksum(hw);
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+ if (status) {
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+ *errno = hw->aq.asq_last_status ?
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+ i40e_aq_rc_to_posix(hw->aq.asq_last_status) :
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+ -EIO;
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+ } else {
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+ hw->aq.nvm_release_on_done = true;
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+ hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
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+ }
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+ break;
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+
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+ default:
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+ status = I40E_NOT_SUPPORTED;
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+ *errno = -ESRCH;
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+ break;
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+ }
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+ return status;
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+}
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+
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+/**
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+ * i40e_nvmupd_validate_command - Validate given command
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+ * @hw: pointer to hardware structure
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+ * @cmd: pointer to nvm update command buffer
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+ * @errno: pointer to return error code
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+ *
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+ * Return one of the valid command types or I40E_NVMUPD_INVALID
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+ **/
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+static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
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+ struct i40e_nvm_access *cmd,
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+ int *errno)
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+{
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+ enum i40e_nvmupd_cmd upd_cmd;
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+ u8 transaction, module;
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+
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+ /* anything that doesn't match a recognized case is an error */
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+ upd_cmd = I40E_NVMUPD_INVALID;
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+
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+ transaction = i40e_nvmupd_get_transaction(cmd->config);
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+ module = i40e_nvmupd_get_module(cmd->config);
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+
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+ /* limits on data size */
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+ if ((cmd->data_size < 1) ||
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+ (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
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|
|
+ hw_dbg(hw, "i40e_nvmupd_validate_command data_size %d\n",
|
|
|
+ cmd->data_size);
|
|
|
+ *errno = -EFAULT;
|
|
|
+ return I40E_NVMUPD_INVALID;
|
|
|
+ }
|
|
|
+
|
|
|
+ switch (cmd->command) {
|
|
|
+ case I40E_NVM_READ:
|
|
|
+ switch (transaction) {
|
|
|
+ case I40E_NVM_CON:
|
|
|
+ upd_cmd = I40E_NVMUPD_READ_CON;
|
|
|
+ break;
|
|
|
+ case I40E_NVM_SNT:
|
|
|
+ upd_cmd = I40E_NVMUPD_READ_SNT;
|
|
|
+ break;
|
|
|
+ case I40E_NVM_LCB:
|
|
|
+ upd_cmd = I40E_NVMUPD_READ_LCB;
|
|
|
+ break;
|
|
|
+ case I40E_NVM_SA:
|
|
|
+ upd_cmd = I40E_NVMUPD_READ_SA;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ break;
|
|
|
+
|
|
|
+ case I40E_NVM_WRITE:
|
|
|
+ switch (transaction) {
|
|
|
+ case I40E_NVM_CON:
|
|
|
+ upd_cmd = I40E_NVMUPD_WRITE_CON;
|
|
|
+ break;
|
|
|
+ case I40E_NVM_SNT:
|
|
|
+ upd_cmd = I40E_NVMUPD_WRITE_SNT;
|
|
|
+ break;
|
|
|
+ case I40E_NVM_LCB:
|
|
|
+ upd_cmd = I40E_NVMUPD_WRITE_LCB;
|
|
|
+ break;
|
|
|
+ case I40E_NVM_SA:
|
|
|
+ upd_cmd = I40E_NVMUPD_WRITE_SA;
|
|
|
+ break;
|
|
|
+ case I40E_NVM_ERA:
|
|
|
+ upd_cmd = I40E_NVMUPD_WRITE_ERA;
|
|
|
+ break;
|
|
|
+ case I40E_NVM_CSUM:
|
|
|
+ upd_cmd = I40E_NVMUPD_CSUM_CON;
|
|
|
+ break;
|
|
|
+ case (I40E_NVM_CSUM|I40E_NVM_SA):
|
|
|
+ upd_cmd = I40E_NVMUPD_CSUM_SA;
|
|
|
+ break;
|
|
|
+ case (I40E_NVM_CSUM|I40E_NVM_LCB):
|
|
|
+ upd_cmd = I40E_NVMUPD_CSUM_LCB;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (upd_cmd == I40E_NVMUPD_INVALID) {
|
|
|
+ *errno = -EFAULT;
|
|
|
+ hw_dbg(hw,
|
|
|
+ "i40e_nvmupd_validate_command returns %d errno: %d\n",
|
|
|
+ upd_cmd, *errno);
|
|
|
+ }
|
|
|
+ return upd_cmd;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * i40e_nvmupd_nvm_read - Read NVM
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ * @cmd: pointer to nvm update command buffer
|
|
|
+ * @bytes: pointer to the data buffer
|
|
|
+ * @errno: pointer to return error code
|
|
|
+ *
|
|
|
+ * cmd structure contains identifiers and data buffer
|
|
|
+ **/
|
|
|
+static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
|
|
|
+ struct i40e_nvm_access *cmd,
|
|
|
+ u8 *bytes, int *errno)
|
|
|
+{
|
|
|
+ i40e_status status;
|
|
|
+ u8 module, transaction;
|
|
|
+ bool last;
|
|
|
+
|
|
|
+ transaction = i40e_nvmupd_get_transaction(cmd->config);
|
|
|
+ module = i40e_nvmupd_get_module(cmd->config);
|
|
|
+ last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
|
|
|
+ hw_dbg(hw, "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n",
|
|
|
+ module, cmd->offset, cmd->data_size);
|
|
|
+
|
|
|
+ status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
|
|
|
+ bytes, last, NULL);
|
|
|
+ hw_dbg(hw, "i40e_nvmupd_nvm_read status %d\n", status);
|
|
|
+ if (status)
|
|
|
+ *errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
|
|
+
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * i40e_nvmupd_nvm_erase - Erase an NVM module
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ * @cmd: pointer to nvm update command buffer
|
|
|
+ * @errno: pointer to return error code
|
|
|
+ *
|
|
|
+ * module, offset, data_size and data are in cmd structure
|
|
|
+ **/
|
|
|
+static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
|
|
|
+ struct i40e_nvm_access *cmd,
|
|
|
+ int *errno)
|
|
|
+{
|
|
|
+ i40e_status status = 0;
|
|
|
+ u8 module, transaction;
|
|
|
+ bool last;
|
|
|
+
|
|
|
+ transaction = i40e_nvmupd_get_transaction(cmd->config);
|
|
|
+ module = i40e_nvmupd_get_module(cmd->config);
|
|
|
+ last = (transaction & I40E_NVM_LCB);
|
|
|
+ hw_dbg(hw, "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n",
|
|
|
+ module, cmd->offset, cmd->data_size);
|
|
|
+ status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
|
|
|
+ last, NULL);
|
|
|
+ hw_dbg(hw, "i40e_nvmupd_nvm_erase status %d\n", status);
|
|
|
+ if (status)
|
|
|
+ *errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
|
|
+
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * i40e_nvmupd_nvm_write - Write NVM
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ * @cmd: pointer to nvm update command buffer
|
|
|
+ * @bytes: pointer to the data buffer
|
|
|
+ * @errno: pointer to return error code
|
|
|
+ *
|
|
|
+ * module, offset, data_size and data are in cmd structure
|
|
|
+ **/
|
|
|
+static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
|
|
|
+ struct i40e_nvm_access *cmd,
|
|
|
+ u8 *bytes, int *errno)
|
|
|
+{
|
|
|
+ i40e_status status = 0;
|
|
|
+ u8 module, transaction;
|
|
|
+ bool last;
|
|
|
+
|
|
|
+ transaction = i40e_nvmupd_get_transaction(cmd->config);
|
|
|
+ module = i40e_nvmupd_get_module(cmd->config);
|
|
|
+ last = (transaction & I40E_NVM_LCB);
|
|
|
+ hw_dbg(hw, "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
|
|
|
+ module, cmd->offset, cmd->data_size);
|
|
|
+ status = i40e_aq_update_nvm(hw, module, cmd->offset,
|
|
|
+ (u16)cmd->data_size, bytes, last, NULL);
|
|
|
+ hw_dbg(hw, "i40e_nvmupd_nvm_write status %d\n", status);
|
|
|
+ if (status)
|
|
|
+ *errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
|
|
+
|
|
|
+ return status;
|
|
|
+}
|
Shannon Nelson