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@@ -338,6 +338,160 @@ out_unlock:
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return err;
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return err;
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}
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}
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+static struct i915_vma *empty_batch(struct drm_i915_private *i915)
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+{
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+ struct drm_i915_gem_object *obj;
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+ struct i915_vma *vma;
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+ u32 *cmd;
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+ int err;
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+
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+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
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+ if (IS_ERR(obj))
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+ return ERR_CAST(obj);
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+
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+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
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+ if (IS_ERR(cmd)) {
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+ err = PTR_ERR(cmd);
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+ goto err;
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+ }
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+ *cmd = MI_BATCH_BUFFER_END;
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+ i915_gem_object_unpin_map(obj);
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+
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+ err = i915_gem_object_set_to_gtt_domain(obj, false);
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+ if (err)
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+ goto err;
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+
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+ vma = i915_vma_instance(obj, &i915->ggtt.base, NULL);
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+ if (IS_ERR(vma)) {
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+ err = PTR_ERR(vma);
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+ goto err;
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+ }
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+
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+ err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_GLOBAL);
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+ if (err)
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+ goto err;
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+
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+ return vma;
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+
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+err:
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+ i915_gem_object_put(obj);
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+ return ERR_PTR(err);
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+}
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+
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+static struct drm_i915_gem_request *
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+empty_request(struct intel_engine_cs *engine,
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+ struct i915_vma *batch)
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+{
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+ struct drm_i915_gem_request *request;
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+ int err;
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+
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+ request = i915_gem_request_alloc(engine,
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+ engine->i915->kernel_context);
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+ if (IS_ERR(request))
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+ return request;
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+
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+ err = engine->emit_flush(request, EMIT_INVALIDATE);
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+ if (err)
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+ goto out_request;
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+
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+ err = i915_switch_context(request);
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+ if (err)
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+ goto out_request;
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+
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+ err = engine->emit_bb_start(request,
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+ batch->node.start,
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+ batch->node.size,
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+ I915_DISPATCH_SECURE);
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+ if (err)
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+ goto out_request;
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+
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+out_request:
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+ __i915_add_request(request, err == 0);
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+ return err ? ERR_PTR(err) : request;
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+}
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+
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+static int live_empty_request(void *arg)
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+{
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+ struct drm_i915_private *i915 = arg;
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+ struct intel_engine_cs *engine;
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+ struct live_test t;
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+ struct i915_vma *batch;
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+ unsigned int id;
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+ int err = 0;
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+
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+ /* Submit various sized batches of empty requests, to each engine
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+ * (individually), and wait for the batch to complete. We can check
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+ * the overhead of submitting requests to the hardware.
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+ */
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+
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+ mutex_lock(&i915->drm.struct_mutex);
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+
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+ batch = empty_batch(i915);
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+ if (IS_ERR(batch)) {
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+ err = PTR_ERR(batch);
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+ goto out_unlock;
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+ }
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+
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+ for_each_engine(engine, i915, id) {
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+ IGT_TIMEOUT(end_time);
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+ struct drm_i915_gem_request *request;
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+ unsigned long n, prime;
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+ ktime_t times[2] = {};
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+
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+ err = begin_live_test(&t, i915, __func__, engine->name);
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+ if (err)
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+ goto out_batch;
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+
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+ /* Warmup / preload */
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+ request = empty_request(engine, batch);
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+ if (IS_ERR(request)) {
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+ err = PTR_ERR(request);
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+ goto out_batch;
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+ }
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+ i915_wait_request(request,
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+ I915_WAIT_LOCKED,
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+ MAX_SCHEDULE_TIMEOUT);
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+
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+ for_each_prime_number_from(prime, 1, 8192) {
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+ times[1] = ktime_get_raw();
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+
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+ for (n = 0; n < prime; n++) {
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+ request = empty_request(engine, batch);
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+ if (IS_ERR(request)) {
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+ err = PTR_ERR(request);
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+ goto out_batch;
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+ }
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+ }
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+ i915_wait_request(request,
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+ I915_WAIT_LOCKED,
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+ MAX_SCHEDULE_TIMEOUT);
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+
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+ times[1] = ktime_sub(ktime_get_raw(), times[1]);
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+ if (prime == 1)
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+ times[0] = times[1];
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+
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+ if (__igt_timeout(end_time, NULL))
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+ break;
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+ }
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+
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+ err = end_live_test(&t);
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+ if (err)
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+ goto out_batch;
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+
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+ pr_info("Batch latencies on %s: 1 = %lluns, %lu = %lluns\n",
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+ engine->name,
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+ ktime_to_ns(times[0]),
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+ prime, div64_u64(ktime_to_ns(times[1]), prime));
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+ }
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+
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+out_batch:
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+ i915_vma_unpin(batch);
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+ i915_vma_put(batch);
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+out_unlock:
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+ mutex_unlock(&i915->drm.struct_mutex);
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+ return err;
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+}
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+
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static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
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static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
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{
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{
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struct i915_gem_context *ctx = i915->kernel_context;
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struct i915_gem_context *ctx = i915->kernel_context;
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@@ -658,6 +812,7 @@ int i915_gem_request_live_selftests(struct drm_i915_private *i915)
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SUBTEST(live_nop_request),
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SUBTEST(live_nop_request),
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SUBTEST(live_all_engines),
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SUBTEST(live_all_engines),
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SUBTEST(live_sequential_engines),
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SUBTEST(live_sequential_engines),
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+ SUBTEST(live_empty_request),
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};
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};
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return i915_subtests(tests, i915);
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return i915_subtests(tests, i915);
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}
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}
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