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@@ -27,6 +27,7 @@
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* Remarks: bit[31:11] and bit[9:6] should be 0
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*/
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#define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
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+#define UGCTRL2_USB0SEL_EHCI 0x00000010
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#define UGCTRL2_USB0SEL_HSUSB 0x00000020
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#define UGCTRL2_USB0SEL_OTG 0x00000030
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#define UGCTRL2_VBUSSEL 0x00000400
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@@ -49,6 +50,14 @@ static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val)
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usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3);
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}
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+static void usbhs_rcar3_set_usbsel(struct usbhs_priv *priv, bool ehci)
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+{
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+ if (ehci)
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+ usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_EHCI);
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+ else
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+ usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_HSUSB);
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+}
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+
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static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
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void __iomem *base, int enable)
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{
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@@ -74,10 +83,14 @@ static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
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struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
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u32 val;
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int timeout = 1000;
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+ bool is_host = false;
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if (enable) {
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usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */
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- usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_HSUSB);
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+ if (priv->edev)
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+ is_host = extcon_get_state(priv->edev, EXTCON_USB_HOST);
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+
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+ usbhs_rcar3_set_usbsel(priv, is_host);
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usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
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do {
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