|
@@ -1342,6 +1342,42 @@ static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
|
|
|
spin_unlock(&pdata->mac_lock);
|
|
|
}
|
|
|
|
|
|
+static int smsc911x_phy_general_power_up(struct smsc911x_data *pdata)
|
|
|
+{
|
|
|
+ int rc = 0;
|
|
|
+
|
|
|
+ if (!pdata->phy_dev)
|
|
|
+ return rc;
|
|
|
+
|
|
|
+ /* If the internal PHY is in General Power-Down mode, all, except the
|
|
|
+ * management interface, is powered-down and stays in that condition as
|
|
|
+ * long as Phy register bit 0.11 is HIGH.
|
|
|
+ *
|
|
|
+ * In that case, clear the bit 0.11, so the PHY powers up and we can
|
|
|
+ * access to the phy registers.
|
|
|
+ */
|
|
|
+ rc = phy_read(pdata->phy_dev, MII_BMCR);
|
|
|
+ if (rc < 0) {
|
|
|
+ SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
|
|
|
+ return rc;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* If the PHY general power-down bit is not set is not necessary to
|
|
|
+ * disable the general power down-mode.
|
|
|
+ */
|
|
|
+ if (rc & BMCR_PDOWN) {
|
|
|
+ rc = phy_write(pdata->phy_dev, MII_BMCR, rc & ~BMCR_PDOWN);
|
|
|
+ if (rc < 0) {
|
|
|
+ SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
|
|
|
+ return rc;
|
|
|
+ }
|
|
|
+
|
|
|
+ usleep_range(1000, 1500);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata)
|
|
|
{
|
|
|
int rc = 0;
|
|
@@ -1407,6 +1443,16 @@ static int smsc911x_soft_reset(struct smsc911x_data *pdata)
|
|
|
unsigned int temp;
|
|
|
int ret;
|
|
|
|
|
|
+ /*
|
|
|
+ * Make sure to power-up the PHY chip before doing a reset, otherwise
|
|
|
+ * the reset fails.
|
|
|
+ */
|
|
|
+ ret = smsc911x_phy_general_power_up(pdata);
|
|
|
+ if (ret) {
|
|
|
+ SMSC_WARN(pdata, drv, "Failed to power-up the PHY chip");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
/*
|
|
|
* LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that
|
|
|
* are initialized in a Energy Detect Power-Down mode that prevents
|