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@@ -61,6 +61,7 @@ enum {
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#define INTEL_MSR_RANGE (0xffff)
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#define AMD_MSR_RANGE (0x7)
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+#define HYGON_MSR_RANGE (0x7)
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#define MSR_K7_HWCR_CPB_DIS (1ULL << 25)
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@@ -95,6 +96,7 @@ static bool boost_state(unsigned int cpu)
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rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi);
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msr = lo | ((u64)hi << 32);
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return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
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+ case X86_VENDOR_HYGON:
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case X86_VENDOR_AMD:
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rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi);
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msr = lo | ((u64)hi << 32);
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@@ -113,6 +115,7 @@ static int boost_set_msr(bool enable)
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msr_addr = MSR_IA32_MISC_ENABLE;
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msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
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break;
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+ case X86_VENDOR_HYGON:
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case X86_VENDOR_AMD:
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msr_addr = MSR_K7_HWCR;
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msr_mask = MSR_K7_HWCR_CPB_DIS;
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@@ -225,6 +228,8 @@ static unsigned extract_msr(struct cpufreq_policy *policy, u32 msr)
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
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msr &= AMD_MSR_RANGE;
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+ else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
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+ msr &= HYGON_MSR_RANGE;
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else
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msr &= INTEL_MSR_RANGE;
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