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@@ -410,6 +410,14 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
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SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
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SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
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}
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}
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+static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
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+{
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+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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+ amdgpu_ring_write(ring, mmHDP_DEBUG0);
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+ amdgpu_ring_write(ring, 1);
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+}
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+
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/**
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/**
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* sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
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* sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
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*
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*
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@@ -1558,6 +1566,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
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.emit_fence = sdma_v3_0_ring_emit_fence,
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.emit_fence = sdma_v3_0_ring_emit_fence,
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.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
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.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
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.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
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.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
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+ .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
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.test_ring = sdma_v3_0_ring_test_ring,
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.test_ring = sdma_v3_0_ring_test_ring,
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.test_ib = sdma_v3_0_ring_test_ib,
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.test_ib = sdma_v3_0_ring_test_ib,
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.insert_nop = sdma_v3_0_ring_insert_nop,
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.insert_nop = sdma_v3_0_ring_insert_nop,
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