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@@ -46,7 +46,7 @@
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#define Cpu2HstMbx1 0x00100F04
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#define MbxStat1 0x00100F08
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#define Stream2Host_Intr_Sts 0x00100F24
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-#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */
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+#define C011_RET_SUCCESS 0x0 /* Return status of firmware command. */
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/* TS input status register */
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#define TS_StreamAFIFOStatus 0x0010044C
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@@ -141,7 +141,7 @@ union link_misc_perst_deco_ctrl {
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uint32_t reserved0:3; /* Reserved.No Effect*/
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uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of
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27MHz clk used to clk BCM7412*/
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- uint32_t reserved1:27; /* Reseved. No Effect*/
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+ uint32_t reserved1:27; /* Reserved. No Effect*/
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};
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uint32_t whole_reg;
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@@ -176,7 +176,7 @@ union link_misc_perst_decoder_ctrl {
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uint32_t res0:3; /* Reserved.No Effect*/
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uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz
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clk used to clk BCM7412*/
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- uint32_t res1:27; /* Reseved. No Effect */
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+ uint32_t res1:27; /* Reserved. No Effect */
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};
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uint32_t whole_reg;
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