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ARM: shmobile: lager: Fix QSPI mode of SPI-Flash into mode3

In order to change into mode3, CPOL and CPHA bit of SPCMD register
of QSPI is changed. Mode3 can avoid intermediate voltage.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
[horms: Updated changelog and re-ordered properties]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Hisashi Nakamura 10 jaren geleden
bovenliggende
commit
cbf4116833
1 gewijzigde bestanden met toevoegingen van 2 en 0 verwijderingen
  1. 2 0
      arch/arm/boot/dts/r8a7790-lager.dts

+ 2 - 0
arch/arm/boot/dts/r8a7790-lager.dts

@@ -397,6 +397,8 @@
 		spi-max-frequency = <30000000>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
+		spi-cpha;
+		spi-cpol;
 		m25p,fast-read;
 
 		partition@0 {