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@@ -505,6 +505,21 @@ extern int kern_addr_valid(unsigned long addr);
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#define pgtable_cache_init() do { } while (0)
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+/*
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+ * On AArch64, the cache coherency is handled via the set_pte_at() function.
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+ */
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+static inline void update_mmu_cache(struct vm_area_struct *vma,
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+ unsigned long addr, pte_t *ptep)
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+{
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+ /*
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+ * set_pte() does not have a DSB for user mappings, so make sure that
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+ * the page table write is visible.
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+ */
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+ dsb(ishst);
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+}
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+
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+#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
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+
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_PGTABLE_H */
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