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@@ -1062,7 +1062,7 @@
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reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
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clocks = <&mp_clk>;
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#clock-cells = <1>;
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- renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
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+ clock-indices = <R8A7791_CLK_MSIOF0>;
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clock-output-names = "msiof0";
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};
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mstp1_clks: mstp1_clks@e6150134 {
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@@ -1073,7 +1073,7 @@
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<&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
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<&zs_clk>;
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#clock-cells = <1>;
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- renesas,clock-indices = <
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+ clock-indices = <
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R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
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R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
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R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
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@@ -1093,7 +1093,7 @@
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<&mp_clk>, <&mp_clk>, <&mp_clk>,
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<&zs_clk>, <&zs_clk>;
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#clock-cells = <1>;
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- renesas,clock-indices = <
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+ clock-indices = <
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R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
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R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
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R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
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@@ -1111,7 +1111,7 @@
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<&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
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<&hp_clk>, <&hp_clk>;
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#clock-cells = <1>;
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- renesas,clock-indices = <
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+ clock-indices = <
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R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
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R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
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R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
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@@ -1127,8 +1127,10 @@
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reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
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clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
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#clock-cells = <1>;
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- renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
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- R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
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+ clock-indices = <
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+ R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
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+ R8A7791_CLK_THERMAL R8A7791_CLK_PWM
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+ >;
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clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
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};
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mstp7_clks: mstp7_clks@e615014c {
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@@ -1138,7 +1140,7 @@
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<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
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<&zx_clk>, <&zx_clk>, <&zx_clk>;
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#clock-cells = <1>;
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- renesas,clock-indices = <
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+ clock-indices = <
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R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
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R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
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R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
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@@ -1155,7 +1157,7 @@
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clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
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<&zs_clk>;
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#clock-cells = <1>;
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- renesas,clock-indices = <
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+ clock-indices = <
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R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
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R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
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>;
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@@ -1171,7 +1173,7 @@
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<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
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<&hp_clk>, <&hp_clk>;
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#clock-cells = <1>;
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- renesas,clock-indices = <
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+ clock-indices = <
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R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
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R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
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R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
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@@ -1221,7 +1223,7 @@
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reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
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clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
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#clock-cells = <1>;
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- renesas,clock-indices = <
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+ clock-indices = <
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R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
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>;
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clock-output-names = "scifa3", "scifa4", "scifa5";
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