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@@ -3634,10 +3634,6 @@ int __init omap3xxx_clk_init(void)
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omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
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omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
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ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
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ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
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omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
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omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
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- } else if (soc_is_am33xx()) {
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- cpu_mask = RATE_IN_AM33XX;
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- } else if (cpu_is_ti814x()) {
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- cpu_mask = RATE_IN_TI814X;
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} else if (cpu_is_omap34xx()) {
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} else if (cpu_is_omap34xx()) {
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if (omap_rev() == OMAP3430_REV_ES1_0) {
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if (omap_rev() == OMAP3430_REV_ES1_0) {
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cpu_mask = RATE_IN_3430ES1;
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cpu_mask = RATE_IN_3430ES1;
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@@ -3681,7 +3677,7 @@ int __init omap3xxx_clk_init(void)
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* Lock DPLL5 -- here only until other device init code can
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* Lock DPLL5 -- here only until other device init code can
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* handle this
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* handle this
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*/
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*/
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- if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
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+ if (omap_rev() >= OMAP3430_REV_ES2_0)
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omap3_clk_lock_dpll5();
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omap3_clk_lock_dpll5();
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/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
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/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
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