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@@ -11,6 +11,7 @@
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#include <linux/host1x.h>
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#include <linux/host1x.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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+#include <linux/reset.h>
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#include <linux/tegra-powergate.h>
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#include <linux/tegra-powergate.h>
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#include "drm.h"
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#include "drm.h"
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@@ -22,6 +23,8 @@ struct gr3d {
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struct host1x_channel *channel;
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struct host1x_channel *channel;
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struct clk *clk_secondary;
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struct clk *clk_secondary;
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struct clk *clk;
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struct clk *clk;
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+ struct reset_control *rst_secondary;
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+ struct reset_control *rst;
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DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
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DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
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};
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};
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@@ -255,12 +258,25 @@ static int gr3d_probe(struct platform_device *pdev)
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return PTR_ERR(gr3d->clk);
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return PTR_ERR(gr3d->clk);
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}
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}
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+ gr3d->rst = devm_reset_control_get(&pdev->dev, "3d");
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+ if (IS_ERR(gr3d->rst)) {
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+ dev_err(&pdev->dev, "cannot get reset\n");
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+ return PTR_ERR(gr3d->rst);
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+ }
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+
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if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
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if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
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gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
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gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
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if (IS_ERR(gr3d->clk)) {
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if (IS_ERR(gr3d->clk)) {
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dev_err(&pdev->dev, "cannot get secondary clock\n");
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dev_err(&pdev->dev, "cannot get secondary clock\n");
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return PTR_ERR(gr3d->clk);
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return PTR_ERR(gr3d->clk);
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}
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}
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+
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+ gr3d->rst_secondary = devm_reset_control_get(&pdev->dev,
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+ "3d2");
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+ if (IS_ERR(gr3d->rst_secondary)) {
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+ dev_err(&pdev->dev, "cannot get secondary reset\n");
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+ return PTR_ERR(gr3d->rst_secondary);
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+ }
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}
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}
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
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