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@@ -56,7 +56,7 @@ static int xgmac_wait_until_free(struct device *dev,
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/* Wait till the bus is free */
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status = spin_event_timeout(
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- !((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY), TIMEOUT, 0);
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+ !((ioread32be(®s->mdio_stat)) & MDIO_STAT_BSY), TIMEOUT, 0);
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if (!status) {
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dev_err(dev, "timeout waiting for bus to be free\n");
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return -ETIMEDOUT;
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@@ -75,7 +75,7 @@ static int xgmac_wait_until_done(struct device *dev,
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/* Wait till the MDIO write is complete */
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status = spin_event_timeout(
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- !((in_be32(®s->mdio_data)) & MDIO_DATA_BSY), TIMEOUT, 0);
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+ !((ioread32be(®s->mdio_data)) & MDIO_DATA_BSY), TIMEOUT, 0);
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if (!status) {
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dev_err(dev, "timeout waiting for operation to complete\n");
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return -ETIMEDOUT;
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@@ -96,7 +96,7 @@ static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 val
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u32 mdio_ctl, mdio_stat;
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int ret;
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- mdio_stat = in_be32(®s->mdio_stat);
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+ mdio_stat = ioread32be(®s->mdio_stat);
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if (regnum & MII_ADDR_C45) {
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/* Clause 45 (ie 10G) */
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dev_addr = (regnum >> 16) & 0x1f;
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@@ -107,7 +107,7 @@ static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 val
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mdio_stat &= ~MDIO_STAT_ENC;
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}
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- out_be32(®s->mdio_stat, mdio_stat);
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+ iowrite32be(mdio_stat, ®s->mdio_stat);
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ret = xgmac_wait_until_free(&bus->dev, regs);
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if (ret)
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@@ -115,11 +115,11 @@ static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 val
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/* Set the port and dev addr */
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mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
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- out_be32(®s->mdio_ctl, mdio_ctl);
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+ iowrite32be(mdio_ctl, ®s->mdio_ctl);
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/* Set the register address */
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if (regnum & MII_ADDR_C45) {
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- out_be32(®s->mdio_addr, regnum & 0xffff);
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+ iowrite32be(regnum & 0xffff, ®s->mdio_addr);
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ret = xgmac_wait_until_free(&bus->dev, regs);
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if (ret)
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@@ -127,7 +127,7 @@ static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 val
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}
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/* Write the value to the register */
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- out_be32(®s->mdio_data, MDIO_DATA(value));
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+ iowrite32be(MDIO_DATA(value), ®s->mdio_data);
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ret = xgmac_wait_until_done(&bus->dev, regs);
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if (ret)
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@@ -150,7 +150,7 @@ static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
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uint16_t value;
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int ret;
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- mdio_stat = in_be32(®s->mdio_stat);
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+ mdio_stat = ioread32be(®s->mdio_stat);
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if (regnum & MII_ADDR_C45) {
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dev_addr = (regnum >> 16) & 0x1f;
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mdio_stat |= MDIO_STAT_ENC;
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@@ -159,7 +159,7 @@ static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
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mdio_stat &= ~MDIO_STAT_ENC;
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}
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- out_be32(®s->mdio_stat, mdio_stat);
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+ iowrite32be(mdio_stat, ®s->mdio_stat);
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ret = xgmac_wait_until_free(&bus->dev, regs);
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if (ret)
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@@ -167,11 +167,11 @@ static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
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- out_be32(®s->mdio_ctl, mdio_ctl);
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+ iowrite32be(mdio_ctl, ®s->mdio_ctl);
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/* Set the register address */
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if (regnum & MII_ADDR_C45) {
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- out_be32(®s->mdio_addr, regnum & 0xffff);
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+ iowrite32be(regnum & 0xffff, ®s->mdio_addr);
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ret = xgmac_wait_until_free(&bus->dev, regs);
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if (ret)
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@@ -179,21 +179,21 @@ static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
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}
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/* Initiate the read */
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- out_be32(®s->mdio_ctl, mdio_ctl | MDIO_CTL_READ);
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+ iowrite32be(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl);
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ret = xgmac_wait_until_done(&bus->dev, regs);
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if (ret)
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return ret;
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/* Return all Fs if nothing was there */
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- if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER) {
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+ if (ioread32be(®s->mdio_stat) & MDIO_STAT_RD_ER) {
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dev_err(&bus->dev,
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"Error while reading PHY%d reg at %d.%hhu\n",
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phy_id, dev_addr, regnum);
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return 0xffff;
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}
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- value = in_be32(®s->mdio_data) & 0xffff;
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+ value = ioread32be(®s->mdio_data) & 0xffff;
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dev_dbg(&bus->dev, "read %04x\n", value);
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return value;
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