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@@ -1128,6 +1128,23 @@ static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
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return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
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}
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+static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
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+{
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+ if (bgate) {
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+ amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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+ AMD_IP_BLOCK_TYPE_VCN,
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+ AMD_PG_STATE_GATE);
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+ smum_send_msg_to_smc_with_parameter(hwmgr,
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+ PPSMC_MSG_PowerDownVcn, 0);
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+ } else {
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+ smum_send_msg_to_smc_with_parameter(hwmgr,
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+ PPSMC_MSG_PowerUpVcn, 0);
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+ amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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+ AMD_IP_BLOCK_TYPE_VCN,
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+ AMD_PG_STATE_UNGATE);
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+ }
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+}
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+
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static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
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.backend_init = smu10_hwmgr_backend_init,
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.backend_fini = smu10_hwmgr_backend_fini,
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@@ -1136,7 +1153,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
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.force_dpm_level = smu10_dpm_force_dpm_level,
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.get_power_state_size = smu10_get_power_state_size,
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.powerdown_uvd = NULL,
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- .powergate_uvd = NULL,
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+ .powergate_uvd = smu10_powergate_vcn,
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.powergate_vce = NULL,
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.get_mclk = smu10_dpm_get_mclk,
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.get_sclk = smu10_dpm_get_sclk,
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