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@@ -451,8 +451,9 @@ static void ni_tio_set_sync_mode(struct ni_gpct *counter)
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unsigned int bits = 0;
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unsigned int reg;
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unsigned int mode;
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- unsigned int clk_src;
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- u64 ps;
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+ unsigned int clk_src = 0;
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+ u64 ps = 0;
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+ int ret;
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bool force_alt_sync;
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/* only m series and 660x variants have counting mode registers */
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@@ -482,9 +483,12 @@ static void ni_tio_set_sync_mode(struct ni_gpct *counter)
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break;
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}
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- ni_tio_generic_clock_src_select(counter, &clk_src);
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- ni_tio_clock_period_ps(counter, clk_src, &ps);
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-
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+ ret = ni_tio_generic_clock_src_select(counter, &clk_src);
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+ if (ret)
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+ return;
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+ ret = ni_tio_clock_period_ps(counter, clk_src, &ps);
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+ if (ret)
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+ return;
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/*
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* It's not clear what we should do if clock_period is unknown, so we
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* are not using the alt sync bit in that case.
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@@ -808,7 +812,7 @@ static int ni_tio_get_clock_src(struct ni_gpct *counter,
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unsigned int *clock_source,
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unsigned int *period_ns)
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{
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- u64 temp64;
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+ u64 temp64 = 0;
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int ret;
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ret = ni_tio_generic_clock_src_select(counter, clock_source);
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