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@@ -34,6 +34,18 @@
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#define OMAP34XX_CM_IDLEST_VAL 1
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+/*
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+ * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
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+ * in the same register at a bit offset of 0x8. The EN_ACK for ICK is
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+ * at an offset of 4 from ICK enable bit.
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+ */
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+#define AM35XX_IPSS_ICK_MASK 0xF
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+#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4
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+#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8
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+#define AM35XX_IPSS_CLK_IDLEST_VAL 0
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+
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+#define AM35XX_ST_IPSS_SHIFT 5
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+
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/**
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* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
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* @clk: struct clk * being enabled
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@@ -146,6 +158,88 @@ const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = {
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.find_companion = omap2_clk_dflt_find_companion,
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};
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+/**
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+ * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS
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+ * @clk: struct clk * being enabled
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+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
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+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
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+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
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+ *
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+ * The interface clocks on AM35xx IPSS reflects the clock idle status
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+ * in the enable register itsel at a bit offset of 4 from the enable
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+ * bit. A value of 1 indicates that clock is enabled.
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+ */
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+static void am35xx_clk_find_idlest(struct clk_hw_omap *clk,
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+ void __iomem **idlest_reg,
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+ u8 *idlest_bit,
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+ u8 *idlest_val)
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+{
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+ *idlest_reg = (__force void __iomem *)(clk->enable_reg);
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+ *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
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+ *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
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+}
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+
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+/**
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+ * am35xx_clk_find_companion - find companion clock to @clk
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+ * @clk: struct clk * to find the companion clock of
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+ * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
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+ * @other_bit: u8 ** to return the companion clock bit shift in
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+ *
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+ * Some clocks don't have companion clocks. For example, modules with
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+ * only an interface clock (such as HECC) don't have a companion
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+ * clock. Right now, this code relies on the hardware exporting a bit
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+ * in the correct companion register that indicates that the
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+ * nonexistent 'companion clock' is active. Future patches will
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+ * associate this type of code with per-module data structures to
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+ * avoid this issue, and remove the casts. No return value.
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+ */
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+static void am35xx_clk_find_companion(struct clk_hw_omap *clk,
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+ void __iomem **other_reg,
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+ u8 *other_bit)
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+{
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+ *other_reg = (__force void __iomem *)(clk->enable_reg);
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+ if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
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+ *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
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+ else
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+ *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
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+}
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+
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+const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = {
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+ .find_idlest = am35xx_clk_find_idlest,
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+ .find_companion = am35xx_clk_find_companion,
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+};
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+
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+/**
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+ * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
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+ * @clk: struct clk * being enabled
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+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
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+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
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+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
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+ *
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+ * The IPSS target CM_IDLEST bit is at a different shift from the
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+ * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg
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+ * and @idlest_bit. No return value.
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+ */
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+static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk,
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+ void __iomem **idlest_reg,
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+ u8 *idlest_bit,
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+ u8 *idlest_val)
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+{
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+ u32 r;
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+
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+ r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
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+ *idlest_reg = (__force void __iomem *)r;
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+ *idlest_bit = AM35XX_ST_IPSS_SHIFT;
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+ *idlest_val = OMAP34XX_CM_IDLEST_VAL;
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+}
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+
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+const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
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+ .allow_idle = omap2_clkt_iclk_allow_idle,
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+ .deny_idle = omap2_clkt_iclk_deny_idle,
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+ .find_idlest = am35xx_clk_ipss_find_idlest,
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+ .find_companion = omap2_clk_dflt_find_companion,
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+};
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+
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static struct ti_dt_clk omap3xxx_clks[] = {
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DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
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DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
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Tero Kristo