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@@ -4416,6 +4416,20 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
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}
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}
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+static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
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+ u32 bitmap)
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+{
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+ u32 data;
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+
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+ if (!bitmap)
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+ return;
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+
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+ data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
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+ data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
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+
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+ WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
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+}
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+
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static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
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{
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u32 data, mask;
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@@ -4436,10 +4450,13 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
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{
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int i, j, k, counter, active_cu_number = 0;
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u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
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+ unsigned disable_masks[4 * 2];
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if (!adev || !cu_info)
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return -EINVAL;
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+ amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
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+
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mutex_lock(&adev->grbm_idx_mutex);
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for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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@@ -4447,6 +4464,9 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
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ao_bitmap = 0;
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counter = 0;
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gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
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+ if (i < 4 && j < 2)
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+ gfx_v9_0_set_user_cu_inactive_bitmap(
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+ adev, disable_masks[i * 2 + j]);
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bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
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cu_info->bitmap[i][j] = bitmap;
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