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+/*
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+ * Copyright (C) 2016 Marvell Technology Group Ltd.
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPLv2 or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This library is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This library is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+/*
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+ * Device Tree file for Marvell Armada AP806.
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+ */
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+
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+/dts-v1/;
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+
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+/ {
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+ model = "Marvell Armada AP806";
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+ compatible = "marvell,armada-ap806";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ psci {
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+ compatible = "arm,psci-0.2";
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+ method = "smc";
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+ };
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+
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+
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+ ap806 {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ compatible = "simple-bus";
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+ interrupt-parent = <&gic>;
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+ ranges;
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+
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+ config-space {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "simple-bus";
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+ ranges = <0x0 0x0 0xf0000000 0x1000000>;
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+
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+ gic: interrupt-controller@210000 {
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+ compatible = "arm,gic-400";
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+ #interrupt-cells = <3>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ interrupt-controller;
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+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ reg = <0x210000 0x10000>,
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+ <0x220000 0x20000>,
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+ <0x240000 0x20000>,
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+ <0x260000 0x20000>;
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+
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+ gic_v2m0: v2m@280000 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x280000 0x1000>;
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+ arm,msi-base-spi = <160>;
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+ arm,msi-num-spis = <32>;
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+ };
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+ gic_v2m1: v2m@290000 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x290000 0x1000>;
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+ arm,msi-base-spi = <192>;
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+ arm,msi-num-spis = <32>;
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+ };
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+ gic_v2m2: v2m@2a0000 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x2a0000 0x1000>;
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+ arm,msi-base-spi = <224>;
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+ arm,msi-num-spis = <32>;
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+ };
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+ gic_v2m3: v2m@2b0000 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x2b0000 0x1000>;
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+ arm,msi-base-spi = <256>;
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+ arm,msi-num-spis = <32>;
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+ };
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+ };
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+
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+ timer {
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+ compatible = "arm,armv8-timer";
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+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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+ };
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+
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+ odmi: odmi@300000 {
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+ compatible = "marvell,odmi-controller";
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+ interrupt-controller;
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+ msi-controller;
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+ marvell,odmi-frames = <4>;
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+ reg = <0x300000 0x4000>,
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+ <0x304000 0x4000>,
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+ <0x308000 0x4000>,
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+ <0x30C000 0x4000>;
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+ marvell,spi-base = <128>, <136>, <144>, <152>;
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+ };
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+
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+ xor0@400000 {
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+ compatible = "marvell,mv-xor-v2";
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+ reg = <0x400000 0x1000>,
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+ <0x410000 0x1000>;
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+ msi-parent = <&gic_v2m0>;
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+ dma-coherent;
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+ };
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+
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+ xor1@420000 {
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+ compatible = "marvell,mv-xor-v2";
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+ reg = <0x420000 0x1000>,
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+ <0x430000 0x1000>;
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+ msi-parent = <&gic_v2m0>;
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+ dma-coherent;
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+ };
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+
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+ xor2@440000 {
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+ compatible = "marvell,mv-xor-v2";
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+ reg = <0x440000 0x1000>,
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+ <0x450000 0x1000>;
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+ msi-parent = <&gic_v2m0>;
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+ dma-coherent;
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+ };
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+
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+ xor3@460000 {
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+ compatible = "marvell,mv-xor-v2";
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+ reg = <0x460000 0x1000>,
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+ <0x470000 0x1000>;
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+ msi-parent = <&gic_v2m0>;
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+ dma-coherent;
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+ };
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+
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+ spi0: spi@510600 {
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+ compatible = "marvell,armada-380-spi";
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+ reg = <0x510600 0x50>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ cell-index = <0>;
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+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ringclk 2>;
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+ status = "disabled";
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+ };
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+
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+ i2c0: i2c@511000 {
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+ compatible = "marvell,mv64xxx-i2c";
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+ reg = <0x511000 0x20>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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+ timeout-ms = <1000>;
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+ clocks = <&ringclk 2>;
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+ status = "disabled";
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+ };
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+
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+ serial@512000 {
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+ compatible = "snps,dw-apb-uart";
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+ reg = <0x512000 0x100>;
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+ reg-shift = <2>;
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+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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+ reg-io-width = <1>;
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+ clocks = <&ringclk 2>;
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+ status = "disabled";
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+ };
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+
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+ serial@512100 {
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+ compatible = "snps,dw-apb-uart";
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+ reg = <0x512100 0x100>;
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+ reg-shift = <2>;
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+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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+ reg-io-width = <1>;
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+ clocks = <&ringclk 2>;
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+ status = "disabled";
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+
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+ };
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+
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+ dfx-server@6f8000 {
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+ compatible = "simple-mfd", "syscon";
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+ reg = <0x6f8000 0x70000>;
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+
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+ coreclk: clk@204 {
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+ compatible = "marvell,armada-ap806-core-clock";
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+ #clock-cells = <1>;
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+ clock-output-names = "ddr", "ring", "cpu";
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+ };
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+
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+ ringclk: clk@250 {
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+ compatible = "marvell,armada-ap806-ring-clock";
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+ #clock-cells = <1>;
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+ clock-output-names = "ring-0", "ring-2",
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+ "ring-3", "ring-4",
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+ "ring-5";
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+ clocks = <&coreclk 1>;
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+ };
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+ };
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+ };
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+ };
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+
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+};
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+
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