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@@ -1500,6 +1500,12 @@ static int arizona_validate_fll(struct arizona_fll *fll,
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{
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unsigned int Fvco_min;
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+ if (fll->fout && Fout != fll->fout) {
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+ arizona_fll_err(fll,
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+ "Can't change output on active FLL\n");
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+ return -EINVAL;
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+ }
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+
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if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
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arizona_fll_err(fll,
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"Can't scale %dMHz in to <=13.5MHz\n",
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@@ -1743,6 +1749,15 @@ static int arizona_enable_fll(struct arizona_fll *fll)
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if (already_enabled < 0)
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return already_enabled;
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+ if (already_enabled) {
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+ /* Facilitate smooth refclk across the transition */
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+ regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x7,
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+ ARIZONA_FLL1_GAIN_MASK, 0);
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+ regmap_update_bits_async(fll->arizona->regmap, fll->base + 1,
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+ ARIZONA_FLL1_FREERUN,
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+ ARIZONA_FLL1_FREERUN);
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+ }
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+
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/*
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* If we have both REFCLK and SYNCCLK then enable both,
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* otherwise apply the SYNCCLK settings to REFCLK.
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@@ -1798,6 +1813,10 @@ static int arizona_enable_fll(struct arizona_fll *fll)
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ARIZONA_FLL1_SYNC_ENA,
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ARIZONA_FLL1_SYNC_ENA);
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+ if (already_enabled)
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+ regmap_update_bits_async(arizona->regmap, fll->base + 1,
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+ ARIZONA_FLL1_FREERUN, 0);
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+
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ret = wait_for_completion_timeout(&fll->ok,
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msecs_to_jiffies(250));
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if (ret == 0)
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