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@@ -88,7 +88,6 @@
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#define MSR_IA32_RTIT_CTL 0x00000570
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#define MSR_IA32_RTIT_CTL 0x00000570
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#define MSR_IA32_RTIT_STATUS 0x00000571
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#define MSR_IA32_RTIT_STATUS 0x00000571
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-#define MSR_IA32_RTIT_STATUS 0x00000571
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#define MSR_IA32_RTIT_ADDR0_A 0x00000580
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#define MSR_IA32_RTIT_ADDR0_A 0x00000580
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#define MSR_IA32_RTIT_ADDR0_B 0x00000581
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#define MSR_IA32_RTIT_ADDR0_B 0x00000581
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#define MSR_IA32_RTIT_ADDR1_A 0x00000582
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#define MSR_IA32_RTIT_ADDR1_A 0x00000582
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