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@@ -384,6 +384,25 @@ err1:
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return r;
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}
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+
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+static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
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+{
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+ release_firmware(adev->gfx.pfp_fw);
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+ adev->gfx.pfp_fw = NULL;
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+ release_firmware(adev->gfx.me_fw);
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+ adev->gfx.me_fw = NULL;
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+ release_firmware(adev->gfx.ce_fw);
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+ adev->gfx.ce_fw = NULL;
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+ release_firmware(adev->gfx.rlc_fw);
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+ adev->gfx.rlc_fw = NULL;
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+ release_firmware(adev->gfx.mec_fw);
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+ adev->gfx.mec_fw = NULL;
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+ release_firmware(adev->gfx.mec2_fw);
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+ adev->gfx.mec2_fw = NULL;
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+
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+ kfree(adev->gfx.rlc.register_list_format);
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+}
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+
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static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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{
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const char *chip_name;
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@@ -1429,6 +1448,7 @@ static int gfx_v9_0_sw_fini(void *handle)
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gfx_v9_0_mec_fini(adev);
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gfx_v9_0_ngg_fini(adev);
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+ gfx_v9_0_free_microcode(adev);
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return 0;
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}
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