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@@ -462,70 +462,38 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci)
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{
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u32 regdata;
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- int ret;
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+ u32 socitype;
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/* Get CC core rev
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- * Chipid is assume to be at offset 0 from regs arg
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+ * Chipid is assume to be at offset 0 from SI_ENUM_BASE
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* For different chiptypes or old sdio hosts w/o chipcommon,
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* other ways of recognition should be added here.
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*/
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- ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
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- ci->c_inf[0].base = SI_ENUM_BASE;
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regdata = brcmf_sdiod_regrl(sdiodev,
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- CORE_CC_REG(ci->c_inf[0].base, chipid),
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+ CORE_CC_REG(SI_ENUM_BASE, chipid),
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NULL);
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ci->chip = regdata & CID_ID_MASK;
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ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
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if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
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ci->chiprev >= 2)
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ci->chip = BCM4339_CHIP_ID;
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- ci->socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
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+ socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
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- brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
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+ brcmf_dbg(INFO, "found %s chip: id=0x%x, rev=%d\n",
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+ socitype == SOCI_SB ? "SB" : "AXI", ci->chip, ci->chiprev);
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- /* Address of cores for new chips should be added here */
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- switch (ci->chip) {
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- case BCM43143_CHIP_ID:
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- ci->c_inf[0].wrapbase = ci->c_inf[0].base + 0x00100000;
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- ci->c_inf[0].cib = 0x2b000000;
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- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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- ci->c_inf[1].base = BCM43143_CORE_BUS_BASE;
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- ci->c_inf[1].wrapbase = ci->c_inf[1].base + 0x00100000;
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- ci->c_inf[1].cib = 0x18000000;
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- ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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- ci->c_inf[2].base = BCM43143_CORE_SOCRAM_BASE;
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- ci->c_inf[2].wrapbase = ci->c_inf[2].base + 0x00100000;
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- ci->c_inf[2].cib = 0x14000000;
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- ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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- ci->c_inf[3].base = BCM43143_CORE_ARM_BASE;
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- ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
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- ci->c_inf[3].cib = 0x07000000;
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- ci->c_inf[4].id = BCMA_CORE_80211;
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- ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
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- ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
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- ci->ramsize = BCM43143_RAMSIZE;
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- break;
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- case BCM43241_CHIP_ID:
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- ci->c_inf[0].wrapbase = 0x18100000;
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- ci->c_inf[0].cib = 0x2a084411;
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- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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- ci->c_inf[1].base = 0x18002000;
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- ci->c_inf[1].wrapbase = 0x18102000;
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- ci->c_inf[1].cib = 0x0e004211;
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- ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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- ci->c_inf[2].base = 0x18004000;
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- ci->c_inf[2].wrapbase = 0x18104000;
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- ci->c_inf[2].cib = 0x14080401;
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- ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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- ci->c_inf[3].base = 0x18003000;
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- ci->c_inf[3].wrapbase = 0x18103000;
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- ci->c_inf[3].cib = 0x07004211;
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- ci->c_inf[4].id = BCMA_CORE_80211;
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- ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
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- ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
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- ci->ramsize = 0x90000;
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- break;
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- case BCM4329_CHIP_ID:
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+ if (socitype == SOCI_SB) {
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+ if (ci->chip != BCM4329_CHIP_ID) {
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+ brcmf_err("SB chip is not supported\n");
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+ return -ENODEV;
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+ }
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+ ci->iscoreup = brcmf_sdio_sb_iscoreup;
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+ ci->corerev = brcmf_sdio_sb_corerev;
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+ ci->coredisable = brcmf_sdio_sb_coredisable;
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+ ci->resetcore = brcmf_sdio_sb_resetcore;
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+
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+ ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
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+ ci->c_inf[0].base = SI_ENUM_BASE;
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ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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ci->c_inf[1].base = BCM4329_CORE_BUS_BASE;
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ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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@@ -535,129 +503,162 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
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ci->c_inf[4].id = BCMA_CORE_80211;
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ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
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ci->ramsize = BCM4329_RAMSIZE;
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- break;
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- case BCM4330_CHIP_ID:
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- ci->c_inf[0].wrapbase = 0x18100000;
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- ci->c_inf[0].cib = 0x27004211;
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- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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- ci->c_inf[1].base = 0x18002000;
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- ci->c_inf[1].wrapbase = 0x18102000;
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- ci->c_inf[1].cib = 0x07004211;
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- ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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- ci->c_inf[2].base = 0x18004000;
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- ci->c_inf[2].wrapbase = 0x18104000;
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- ci->c_inf[2].cib = 0x0d080401;
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- ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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- ci->c_inf[3].base = 0x18003000;
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- ci->c_inf[3].wrapbase = 0x18103000;
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- ci->c_inf[3].cib = 0x03004211;
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- ci->c_inf[4].id = BCMA_CORE_80211;
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- ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
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- ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
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- ci->ramsize = 0x48000;
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- break;
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- case BCM4334_CHIP_ID:
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- ci->c_inf[0].wrapbase = 0x18100000;
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- ci->c_inf[0].cib = 0x29004211;
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- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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- ci->c_inf[1].base = 0x18002000;
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- ci->c_inf[1].wrapbase = 0x18102000;
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- ci->c_inf[1].cib = 0x0d004211;
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- ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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- ci->c_inf[2].base = 0x18004000;
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- ci->c_inf[2].wrapbase = 0x18104000;
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- ci->c_inf[2].cib = 0x13080401;
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- ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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- ci->c_inf[3].base = 0x18003000;
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- ci->c_inf[3].wrapbase = 0x18103000;
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- ci->c_inf[3].cib = 0x07004211;
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- ci->c_inf[4].id = BCMA_CORE_80211;
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- ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
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- ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
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- ci->ramsize = 0x80000;
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- break;
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- case BCM4335_CHIP_ID:
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- ci->c_inf[0].wrapbase = 0x18100000;
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- ci->c_inf[0].cib = 0x2b084411;
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- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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- ci->c_inf[1].base = 0x18005000;
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- ci->c_inf[1].wrapbase = 0x18105000;
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- ci->c_inf[1].cib = 0x0f004211;
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- ci->c_inf[2].id = BCMA_CORE_ARM_CR4;
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- ci->c_inf[2].base = 0x18002000;
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- ci->c_inf[2].wrapbase = 0x18102000;
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- ci->c_inf[2].cib = 0x01084411;
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- ci->c_inf[3].id = BCMA_CORE_80211;
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- ci->c_inf[3].base = BCM43xx_CORE_D11_BASE;
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- ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
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- ci->ramsize = 0xc0000;
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- ci->rambase = 0x180000;
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- break;
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- case BCM4339_CHIP_ID:
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- ci->c_inf[0].wrapbase = 0x18100000;
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- ci->c_inf[0].cib = 0x2e084411;
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- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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- ci->c_inf[1].base = 0x18005000;
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- ci->c_inf[1].wrapbase = 0x18105000;
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- ci->c_inf[1].cib = 0x15004211;
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- ci->c_inf[2].id = BCMA_CORE_ARM_CR4;
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- ci->c_inf[2].base = 0x18002000;
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- ci->c_inf[2].wrapbase = 0x18102000;
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- ci->c_inf[2].cib = 0x04084411;
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- ci->c_inf[3].id = BCMA_CORE_80211;
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- ci->c_inf[3].base = BCM43xx_CORE_D11_BASE;
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- ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
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- ci->ramsize = 0xc0000;
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- ci->rambase = 0x180000;
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- break;
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- case BCM43362_CHIP_ID:
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- ci->c_inf[0].wrapbase = 0x18100000;
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- ci->c_inf[0].cib = 0x27004211;
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- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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- ci->c_inf[1].base = 0x18002000;
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- ci->c_inf[1].wrapbase = 0x18102000;
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- ci->c_inf[1].cib = 0x0a004211;
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- ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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- ci->c_inf[2].base = 0x18004000;
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- ci->c_inf[2].wrapbase = 0x18104000;
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- ci->c_inf[2].cib = 0x08080401;
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- ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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- ci->c_inf[3].base = 0x18003000;
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- ci->c_inf[3].wrapbase = 0x18103000;
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- ci->c_inf[3].cib = 0x03004211;
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- ci->c_inf[4].id = BCMA_CORE_80211;
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- ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
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- ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
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- ci->ramsize = 0x3C000;
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- break;
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- default:
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- brcmf_err("chipid 0x%x is not supported\n", ci->chip);
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- return -ENODEV;
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- }
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-
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- ret = brcmf_sdio_chip_cichk(ci);
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- if (ret)
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- return ret;
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-
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- switch (ci->socitype) {
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- case SOCI_SB:
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- ci->iscoreup = brcmf_sdio_sb_iscoreup;
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- ci->corerev = brcmf_sdio_sb_corerev;
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- ci->coredisable = brcmf_sdio_sb_coredisable;
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- ci->resetcore = brcmf_sdio_sb_resetcore;
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- break;
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- case SOCI_AI:
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+ } else if (socitype == SOCI_AI) {
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ci->iscoreup = brcmf_sdio_ai_iscoreup;
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ci->corerev = brcmf_sdio_ai_corerev;
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ci->coredisable = brcmf_sdio_ai_coredisable;
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ci->resetcore = brcmf_sdio_ai_resetcore;
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- break;
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- default:
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- brcmf_err("socitype %u not supported\n", ci->socitype);
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+
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+ ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
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+ ci->c_inf[0].base = SI_ENUM_BASE;
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+
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+ /* Address of cores for new chips should be added here */
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+ switch (ci->chip) {
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+ case BCM43143_CHIP_ID:
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+ ci->c_inf[0].wrapbase = ci->c_inf[0].base + 0x00100000;
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+ ci->c_inf[0].cib = 0x2b000000;
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+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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+ ci->c_inf[1].base = BCM43143_CORE_BUS_BASE;
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+ ci->c_inf[1].wrapbase = ci->c_inf[1].base + 0x00100000;
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+ ci->c_inf[1].cib = 0x18000000;
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+ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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+ ci->c_inf[2].base = BCM43143_CORE_SOCRAM_BASE;
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+ ci->c_inf[2].wrapbase = ci->c_inf[2].base + 0x00100000;
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+ ci->c_inf[2].cib = 0x14000000;
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+ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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+ ci->c_inf[3].base = BCM43143_CORE_ARM_BASE;
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+ ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
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+ ci->c_inf[3].cib = 0x07000000;
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+ ci->c_inf[4].id = BCMA_CORE_80211;
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+ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
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+ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
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+ ci->ramsize = BCM43143_RAMSIZE;
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+ break;
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+ case BCM43241_CHIP_ID:
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+ ci->c_inf[0].wrapbase = 0x18100000;
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+ ci->c_inf[0].cib = 0x2a084411;
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+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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+ ci->c_inf[1].base = 0x18002000;
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+ ci->c_inf[1].wrapbase = 0x18102000;
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+ ci->c_inf[1].cib = 0x0e004211;
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+ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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+ ci->c_inf[2].base = 0x18004000;
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+ ci->c_inf[2].wrapbase = 0x18104000;
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+ ci->c_inf[2].cib = 0x14080401;
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+ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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+ ci->c_inf[3].base = 0x18003000;
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+ ci->c_inf[3].wrapbase = 0x18103000;
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+ ci->c_inf[3].cib = 0x07004211;
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+ ci->c_inf[4].id = BCMA_CORE_80211;
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+ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
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+ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
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+ ci->ramsize = 0x90000;
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+ break;
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+ case BCM4330_CHIP_ID:
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+ ci->c_inf[0].wrapbase = 0x18100000;
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+ ci->c_inf[0].cib = 0x27004211;
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+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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+ ci->c_inf[1].base = 0x18002000;
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+ ci->c_inf[1].wrapbase = 0x18102000;
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+ ci->c_inf[1].cib = 0x07004211;
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+ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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+ ci->c_inf[2].base = 0x18004000;
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+ ci->c_inf[2].wrapbase = 0x18104000;
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+ ci->c_inf[2].cib = 0x0d080401;
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+ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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+ ci->c_inf[3].base = 0x18003000;
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+ ci->c_inf[3].wrapbase = 0x18103000;
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+ ci->c_inf[3].cib = 0x03004211;
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+ ci->c_inf[4].id = BCMA_CORE_80211;
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+ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
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+ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
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+ ci->ramsize = 0x48000;
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+ break;
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+ case BCM4334_CHIP_ID:
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+ ci->c_inf[0].wrapbase = 0x18100000;
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+ ci->c_inf[0].cib = 0x29004211;
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+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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+ ci->c_inf[1].base = 0x18002000;
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+ ci->c_inf[1].wrapbase = 0x18102000;
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+ ci->c_inf[1].cib = 0x0d004211;
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+ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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+ ci->c_inf[2].base = 0x18004000;
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+ ci->c_inf[2].wrapbase = 0x18104000;
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+ ci->c_inf[2].cib = 0x13080401;
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+ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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+ ci->c_inf[3].base = 0x18003000;
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+ ci->c_inf[3].wrapbase = 0x18103000;
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+ ci->c_inf[3].cib = 0x07004211;
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|
|
+ ci->c_inf[4].id = BCMA_CORE_80211;
|
|
|
+ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
|
|
|
+ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
|
|
|
+ ci->ramsize = 0x80000;
|
|
|
+ break;
|
|
|
+ case BCM4335_CHIP_ID:
|
|
|
+ ci->c_inf[0].wrapbase = 0x18100000;
|
|
|
+ ci->c_inf[0].cib = 0x2b084411;
|
|
|
+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
|
|
|
+ ci->c_inf[1].base = 0x18005000;
|
|
|
+ ci->c_inf[1].wrapbase = 0x18105000;
|
|
|
+ ci->c_inf[1].cib = 0x0f004211;
|
|
|
+ ci->c_inf[2].id = BCMA_CORE_ARM_CR4;
|
|
|
+ ci->c_inf[2].base = 0x18002000;
|
|
|
+ ci->c_inf[2].wrapbase = 0x18102000;
|
|
|
+ ci->c_inf[2].cib = 0x01084411;
|
|
|
+ ci->c_inf[3].id = BCMA_CORE_80211;
|
|
|
+ ci->c_inf[3].base = BCM43xx_CORE_D11_BASE;
|
|
|
+ ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
|
|
|
+ ci->ramsize = 0xc0000;
|
|
|
+ ci->rambase = 0x180000;
|
|
|
+ break;
|
|
|
+ case BCM43362_CHIP_ID:
|
|
|
+ ci->c_inf[0].wrapbase = 0x18100000;
|
|
|
+ ci->c_inf[0].cib = 0x27004211;
|
|
|
+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
|
|
|
+ ci->c_inf[1].base = 0x18002000;
|
|
|
+ ci->c_inf[1].wrapbase = 0x18102000;
|
|
|
+ ci->c_inf[1].cib = 0x0a004211;
|
|
|
+ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
|
|
|
+ ci->c_inf[2].base = 0x18004000;
|
|
|
+ ci->c_inf[2].wrapbase = 0x18104000;
|
|
|
+ ci->c_inf[2].cib = 0x08080401;
|
|
|
+ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
|
|
|
+ ci->c_inf[3].base = 0x18003000;
|
|
|
+ ci->c_inf[3].wrapbase = 0x18103000;
|
|
|
+ ci->c_inf[3].cib = 0x03004211;
|
|
|
+ ci->c_inf[4].id = BCMA_CORE_80211;
|
|
|
+ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
|
|
|
+ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
|
|
|
+ ci->ramsize = 0x3C000;
|
|
|
+ break;
|
|
|
+ case BCM4339_CHIP_ID:
|
|
|
+ ci->c_inf[0].wrapbase = 0x18100000;
|
|
|
+ ci->c_inf[0].cib = 0x2e084411;
|
|
|
+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
|
|
|
+ ci->c_inf[1].base = 0x18005000;
|
|
|
+ ci->c_inf[1].wrapbase = 0x18105000;
|
|
|
+ ci->c_inf[1].cib = 0x15004211;
|
|
|
+ ci->c_inf[2].id = BCMA_CORE_ARM_CR4;
|
|
|
+ ci->c_inf[2].base = 0x18002000;
|
|
|
+ ci->c_inf[2].wrapbase = 0x18102000;
|
|
|
+ ci->c_inf[2].cib = 0x04084411;
|
|
|
+ ci->c_inf[3].id = BCMA_CORE_80211;
|
|
|
+ ci->c_inf[3].base = BCM43xx_CORE_D11_BASE;
|
|
|
+ ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
|
|
|
+ ci->ramsize = 0xc0000;
|
|
|
+ ci->rambase = 0x180000;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ brcmf_err("AXI chip is not supported\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ brcmf_err("chip backplane type %u is not supported\n",
|
|
|
+ socitype);
|
|
|
return -ENODEV;
|
|
|
}
|
|
|
|
|
|
- return 0;
|
|
|
+ return brcmf_sdio_chip_cichk(ci);
|
|
|
}
|
|
|
|
|
|
static int
|