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@@ -193,7 +193,8 @@ struct tegra_i2c_dev {
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bool is_multimaster_mode;
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};
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-static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
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+static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
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+ unsigned long reg)
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{
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writel(val, i2c_dev->base + reg);
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}
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@@ -643,9 +644,10 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
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return 0;
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/*
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- * NACK interrupt is generated before the I2C controller generates the
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- * STOP condition on the bus. So wait for 2 clock periods before resetting
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- * the controller so that STOP condition has been delivered properly.
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+ * NACK interrupt is generated before the I2C controller generates
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+ * the STOP condition on the bus. So wait for 2 clock periods
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+ * before resetting the controller so that the STOP condition has
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+ * been delivered properly.
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*/
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if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
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udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
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