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+/* QLogic qed NIC Driver
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+ * Copyright (c) 2015-2017 QLogic Corporation
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+ *
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+ * This software is available to you under a choice of one of two
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+ * licenses. You may choose to be licensed under the terms of the GNU
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+ * General Public License (GPL) Version 2, available from the file
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+ * COPYING in the main directory of this source tree, or the
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+ * OpenIB.org BSD license below:
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+ *
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+ * Redistribution and use in source and binary forms, with or
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+ * without modification, are permitted provided that the following
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+ * conditions are met:
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+ *
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+ * - Redistributions of source code must retain the above
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+ * copyright notice, this list of conditions and the following
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+ * disclaimer.
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+ *
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+ * - Redistributions in binary form must reproduce the above
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+ * copyright notice, this list of conditions and the following
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+ * disclaimer in the documentation and /or other materials
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+ * provided with the distribution.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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+ * SOFTWARE.
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+ */
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+#include <linux/types.h>
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+#include "qed.h"
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+#include "qed_dev_api.h"
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+#include "qed_hw.h"
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+#include "qed_l2.h"
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+#include "qed_ptp.h"
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+#include "qed_reg_addr.h"
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+
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+/* 16 nano second time quantas to wait before making a Drift adjustment */
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+#define QED_DRIFT_CNTR_TIME_QUANTA_SHIFT 0
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+/* Nano seconds to add/subtract when making a Drift adjustment */
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+#define QED_DRIFT_CNTR_ADJUSTMENT_SHIFT 28
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+/* Add/subtract the Adjustment_Value when making a Drift adjustment */
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+#define QED_DRIFT_CNTR_DIRECTION_SHIFT 31
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+#define QED_TIMESTAMP_MASK BIT(16)
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+
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+/* Read Rx timestamp */
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+static int qed_ptp_hw_read_rx_ts(struct qed_dev *cdev, u64 *timestamp)
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+{
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+ struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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+ struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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+ u32 val;
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+
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+ *timestamp = 0;
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+ val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID);
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+ if (!(val & QED_TIMESTAMP_MASK)) {
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+ DP_INFO(p_hwfn, "Invalid Rx timestamp, buf_seqid = %d\n", val);
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+ return -EINVAL;
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+ }
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+
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+ val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_LSB);
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+ *timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_MSB);
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+ *timestamp <<= 32;
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+ *timestamp |= val;
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+
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+ /* Reset timestamp register to allow new timestamp */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
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+ QED_TIMESTAMP_MASK);
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+
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+ return 0;
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+}
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+
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+/* Read Tx timestamp */
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+static int qed_ptp_hw_read_tx_ts(struct qed_dev *cdev, u64 *timestamp)
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+{
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+ struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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+ struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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+ u32 val;
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+
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+ *timestamp = 0;
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+ val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID);
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+ if (!(val & QED_TIMESTAMP_MASK)) {
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+ DP_INFO(p_hwfn, "Invalid Tx timestamp, buf_seqid = %d\n", val);
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+ return -EINVAL;
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+ }
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+
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+ val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_LSB);
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+ *timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_MSB);
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+ *timestamp <<= 32;
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+ *timestamp |= val;
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+
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+ /* Reset timestamp register to allow new timestamp */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
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+
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+ return 0;
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+}
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+
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+/* Read Phy Hardware Clock */
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+static int qed_ptp_hw_read_cc(struct qed_dev *cdev, u64 *phc_cycles)
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+{
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+ struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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+ struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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+ u32 temp = 0;
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+
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+ temp = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_LSB);
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+ *phc_cycles = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_MSB);
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+ *phc_cycles <<= 32;
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+ *phc_cycles |= temp;
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+
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+ return 0;
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+}
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+
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+/* Filter PTP protocol packets that need to be timestamped */
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+static int qed_ptp_hw_cfg_rx_filters(struct qed_dev *cdev,
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+ enum qed_ptp_filter_type type)
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+{
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+ struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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+ struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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+ u32 rule_mask, parm_mask;
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+
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+ switch (type) {
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+ case QED_PTP_FILTER_L2_IPV4_IPV6:
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+ parm_mask = 0x6AA;
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+ rule_mask = 0x3EEE;
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+ break;
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+ case QED_PTP_FILTER_L2:
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+ parm_mask = 0x6BF;
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+ rule_mask = 0x3EFF;
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+ break;
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+ case QED_PTP_FILTER_IPV4_IPV6:
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+ parm_mask = 0x7EA;
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+ rule_mask = 0x3FFE;
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+ break;
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+ case QED_PTP_FILTER_IPV4:
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+ parm_mask = 0x7EE;
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+ rule_mask = 0x3FFE;
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+ break;
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+ default:
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+ DP_INFO(p_hwfn, "Invalid PTP filter type %d\n", type);
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+ return -EINVAL;
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+ }
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+
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, parm_mask);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, rule_mask);
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+
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_TO_HOST, 0x1);
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+
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+ /* Reset possibly old timestamps */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
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+ QED_TIMESTAMP_MASK);
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+
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+ return 0;
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+}
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+
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+/* Adjust the HW clock by a rate given in parts-per-billion (ppb) units.
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+ * FW/HW accepts the adjustment value in terms of 3 parameters:
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+ * Drift period - adjustment happens once in certain number of nano seconds.
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+ * Drift value - time is adjusted by a certain value, for example by 5 ns.
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+ * Drift direction - add or subtract the adjustment value.
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+ * The routine translates ppb into the adjustment triplet in an optimal manner.
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+ */
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+static int qed_ptp_hw_adjfreq(struct qed_dev *cdev, s32 ppb)
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+{
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+ s64 best_val = 0, val, best_period = 0, period, approx_dev, dif, dif2;
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+ struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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+ struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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+ u32 drift_ctr_cfg = 0, drift_state;
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+ int drift_dir = 1;
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+
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+ if (ppb < 0) {
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+ ppb = -ppb;
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+ drift_dir = 0;
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+ }
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+
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+ if (ppb > 1) {
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+ s64 best_dif = ppb, best_approx_dev = 1;
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+
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+ /* Adjustment value is up to +/-7ns, find an optimal value in
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+ * this range.
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+ */
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+ for (val = 7; val > 0; val--) {
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+ period = div_s64(val * 1000000000, ppb);
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+ period -= 8;
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+ period >>= 4;
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+ if (period < 1)
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+ period = 1;
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+ if (period > 0xFFFFFFE)
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+ period = 0xFFFFFFE;
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+
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+ /* Check both rounding ends for approximate error */
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+ approx_dev = period * 16 + 8;
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+ dif = ppb * approx_dev - val * 1000000000;
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+ dif2 = dif + 16 * ppb;
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+
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+ if (dif < 0)
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+ dif = -dif;
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+ if (dif2 < 0)
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+ dif2 = -dif2;
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+
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+ /* Determine which end gives better approximation */
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+ if (dif * (approx_dev + 16) > dif2 * approx_dev) {
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+ period++;
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+ approx_dev += 16;
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+ dif = dif2;
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+ }
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+
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+ /* Track best approximation found so far */
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+ if (best_dif * approx_dev > dif * best_approx_dev) {
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+ best_dif = dif;
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+ best_val = val;
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+ best_period = period;
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+ best_approx_dev = approx_dev;
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+ }
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+ }
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+ } else if (ppb == 1) {
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+ /* This is a special case as its the only value which wouldn't
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+ * fit in a s64 variable. In order to prevent castings simple
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+ * handle it seperately.
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+ */
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+ best_val = 4;
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+ best_period = 0xee6b27f;
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+ } else {
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+ best_val = 0;
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+ best_period = 0xFFFFFFF;
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+ }
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+
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+ drift_ctr_cfg = (best_period << QED_DRIFT_CNTR_TIME_QUANTA_SHIFT) |
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+ (((int)best_val) << QED_DRIFT_CNTR_ADJUSTMENT_SHIFT) |
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+ (((int)drift_dir) << QED_DRIFT_CNTR_DIRECTION_SHIFT);
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+
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x1);
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+
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+ drift_state = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR);
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+ if (drift_state & 1) {
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF,
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+ drift_ctr_cfg);
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+ } else {
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+ DP_INFO(p_hwfn, "Drift counter is not reset\n");
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+ return -EINVAL;
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+ }
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+
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
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+
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+ return 0;
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+}
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+
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+static int qed_ptp_hw_enable(struct qed_dev *cdev)
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+{
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+ struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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+ struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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+
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+ /* Reset PTP event detection rules - will be configured in the IOCTL */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
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+
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 7);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 7);
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+
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TS_OUTPUT_ENABLE_PDA, 0x1);
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+
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+ /* Pause free running counter */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 2);
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+
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_LSB, 0);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_MSB, 0);
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+ /* Resume free running counter */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 4);
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+
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+ /* Disable drift register */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF, 0x0);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
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+
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+ /* Reset possibly old timestamps */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
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+ QED_TIMESTAMP_MASK);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
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+
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+ return 0;
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+}
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+
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+static int qed_ptp_hw_hwtstamp_tx_on(struct qed_dev *cdev)
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+{
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+ struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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+ struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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+
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x6AA);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3EEE);
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+
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+ return 0;
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+}
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+
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+static int qed_ptp_hw_disable(struct qed_dev *cdev)
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+{
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+ struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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+ struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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+
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+ /* Reset PTP event detection rules */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
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+
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
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+
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+ /* Disable the PTP feature */
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 0x0);
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+ qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 0x0);
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+
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+ return 0;
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+}
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+
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+const struct qed_eth_ptp_ops qed_ptp_ops_pass = {
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+ .hwtstamp_tx_on = qed_ptp_hw_hwtstamp_tx_on,
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+ .cfg_rx_filters = qed_ptp_hw_cfg_rx_filters,
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+ .read_rx_ts = qed_ptp_hw_read_rx_ts,
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+ .read_tx_ts = qed_ptp_hw_read_tx_ts,
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+ .read_cc = qed_ptp_hw_read_cc,
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+ .adjfreq = qed_ptp_hw_adjfreq,
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+ .disable = qed_ptp_hw_disable,
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+ .enable = qed_ptp_hw_enable,
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+};
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Sudarsana Reddy Kalluru