drm/nouveau/ltc: cosmetic changes

This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h

@@ -6,7 +6,7 @@ struct nvkm_mm_node;
 #define NVKM_LTC_MAX_ZBC_CNT 16
 
 struct nvkm_ltc {
-	struct nvkm_subdev base;
+	struct nvkm_subdev subdev;
 
 	int  (*tags_alloc)(struct nvkm_ltc *, u32 count,
 			   struct nvkm_mm_node **);

drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c

@@ -24,12 +24,12 @@
 #include "priv.h"
 
 static int
-nvkm_ltc_tags_alloc(struct nvkm_ltc *ltc, u32 n, struct nvkm_mm_node **pnode)
+nvkm_ltc_tags_alloc(struct nvkm_ltc *obj, u32 n, struct nvkm_mm_node **pnode)
 {
-	struct nvkm_ltc_priv *priv = (void *)ltc;
+	struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
 	int ret;
 
-	ret = nvkm_mm_head(&priv->tags, 0, 1, n, n, 1, pnode);
+	ret = nvkm_mm_head(&ltc->tags, 0, 1, n, n, 1, pnode);
 	if (ret)
 		*pnode = NULL;
 
@@ -37,59 +37,59 @@ nvkm_ltc_tags_alloc(struct nvkm_ltc *ltc, u32 n, struct nvkm_mm_node **pnode)
 }
 
 static void
-nvkm_ltc_tags_free(struct nvkm_ltc *ltc, struct nvkm_mm_node **pnode)
+nvkm_ltc_tags_free(struct nvkm_ltc *obj, struct nvkm_mm_node **pnode)
 {
-	struct nvkm_ltc_priv *priv = (void *)ltc;
-	nvkm_mm_free(&priv->tags, pnode);
+	struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
+	nvkm_mm_free(&ltc->tags, pnode);
 }
 
 static void
-nvkm_ltc_tags_clear(struct nvkm_ltc *ltc, u32 first, u32 count)
+nvkm_ltc_tags_clear(struct nvkm_ltc *obj, u32 first, u32 count)
 {
+	struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
 	const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
-	struct nvkm_ltc_priv *priv = (void *)ltc;
 	const u32 limit = first + count - 1;
 
-	BUG_ON((first > limit) || (limit >= priv->num_tags));
+	BUG_ON((first > limit) || (limit >= ltc->num_tags));
 
-	impl->cbc_clear(priv, first, limit);
-	impl->cbc_wait(priv);
+	impl->cbc_clear(ltc, first, limit);
+	impl->cbc_wait(ltc);
 }
 
 static int
-nvkm_ltc_zbc_color_get(struct nvkm_ltc *ltc, int index, const u32 color[4])
+nvkm_ltc_zbc_color_get(struct nvkm_ltc *obj, int index, const u32 color[4])
 {
+	struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
 	const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
-	struct nvkm_ltc_priv *priv = (void *)ltc;
-	memcpy(priv->zbc_color[index], color, sizeof(priv->zbc_color[index]));
-	impl->zbc_clear_color(priv, index, color);
+	memcpy(ltc->zbc_color[index], color, sizeof(ltc->zbc_color[index]));
+	impl->zbc_clear_color(ltc, index, color);
 	return index;
 }
 
 static int
-nvkm_ltc_zbc_depth_get(struct nvkm_ltc *ltc, int index, const u32 depth)
+nvkm_ltc_zbc_depth_get(struct nvkm_ltc *obj, int index, const u32 depth)
 {
+	struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
 	const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
-	struct nvkm_ltc_priv *priv = (void *)ltc;
-	priv->zbc_depth[index] = depth;
-	impl->zbc_clear_depth(priv, index, depth);
+	ltc->zbc_depth[index] = depth;
+	impl->zbc_clear_depth(ltc, index, depth);
 	return index;
 }
 
 int
 _nvkm_ltc_init(struct nvkm_object *object)
 {
+	struct nvkm_ltc_priv *ltc = (void *)object;
 	const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object);
-	struct nvkm_ltc_priv *priv = (void *)object;
 	int ret, i;
 
-	ret = nvkm_subdev_init(&priv->base.base);
+	ret = nvkm_subdev_init(&ltc->base.subdev);
 	if (ret)
 		return ret;
 
-	for (i = priv->base.zbc_min; i <= priv->base.zbc_max; i++) {
-		impl->zbc_clear_color(priv, i, priv->zbc_color[i]);
-		impl->zbc_clear_depth(priv, i, priv->zbc_depth[i]);
+	for (i = ltc->base.zbc_min; i <= ltc->base.zbc_max; i++) {
+		impl->zbc_clear_color(ltc, i, ltc->zbc_color[i]);
+		impl->zbc_clear_depth(ltc, i, ltc->zbc_depth[i]);
 	}
 
 	return 0;
@@ -100,25 +100,25 @@ nvkm_ltc_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 		 struct nvkm_oclass *oclass, int length, void **pobject)
 {
 	const struct nvkm_ltc_impl *impl = (void *)oclass;
-	struct nvkm_ltc_priv *priv;
+	struct nvkm_ltc_priv *ltc;
 	int ret;
 
 	ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PLTCG",
 				  "l2c", length, pobject);
-	priv = *pobject;
+	ltc = *pobject;
 	if (ret)
 		return ret;
 
-	memset(priv->zbc_color, 0x00, sizeof(priv->zbc_color));
-	memset(priv->zbc_depth, 0x00, sizeof(priv->zbc_depth));
-
-	priv->base.base.intr = impl->intr;
-	priv->base.tags_alloc = nvkm_ltc_tags_alloc;
-	priv->base.tags_free = nvkm_ltc_tags_free;
-	priv->base.tags_clear = nvkm_ltc_tags_clear;
-	priv->base.zbc_min = 1; /* reserve 0 for disabled */
-	priv->base.zbc_max = min(impl->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1;
-	priv->base.zbc_color_get = nvkm_ltc_zbc_color_get;
-	priv->base.zbc_depth_get = nvkm_ltc_zbc_depth_get;
+	memset(ltc->zbc_color, 0x00, sizeof(ltc->zbc_color));
+	memset(ltc->zbc_depth, 0x00, sizeof(ltc->zbc_depth));
+
+	ltc->base.subdev.intr = impl->intr;
+	ltc->base.tags_alloc = nvkm_ltc_tags_alloc;
+	ltc->base.tags_free = nvkm_ltc_tags_free;
+	ltc->base.tags_clear = nvkm_ltc_tags_clear;
+	ltc->base.zbc_min = 1; /* reserve 0 for disabled */
+	ltc->base.zbc_max = min(impl->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1;
+	ltc->base.zbc_color_get = nvkm_ltc_zbc_color_get;
+	ltc->base.zbc_depth_get = nvkm_ltc_zbc_depth_get;
 	return 0;
 }

drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c

@@ -28,38 +28,38 @@
 #include <subdev/timer.h>
 
 void
-gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
+gf100_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit)
 {
-	nv_wr32(priv, 0x17e8cc, start);
-	nv_wr32(priv, 0x17e8d0, limit);
-	nv_wr32(priv, 0x17e8c8, 0x00000004);
+	nv_wr32(ltc, 0x17e8cc, start);
+	nv_wr32(ltc, 0x17e8d0, limit);
+	nv_wr32(ltc, 0x17e8c8, 0x00000004);
 }
 
 void
-gf100_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
+gf100_ltc_cbc_wait(struct nvkm_ltc_priv *ltc)
 {
 	int c, s;
-	for (c = 0; c < priv->ltc_nr; c++) {
-		for (s = 0; s < priv->lts_nr; s++)
-			nv_wait(priv, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0);
+	for (c = 0; c < ltc->ltc_nr; c++) {
+		for (s = 0; s < ltc->lts_nr; s++)
+			nv_wait(ltc, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0);
 	}
 }
 
 void
-gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4])
+gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4])
 {
-	nv_mask(priv, 0x17ea44, 0x0000000f, i);
-	nv_wr32(priv, 0x17ea48, color[0]);
-	nv_wr32(priv, 0x17ea4c, color[1]);
-	nv_wr32(priv, 0x17ea50, color[2]);
-	nv_wr32(priv, 0x17ea54, color[3]);
+	nv_mask(ltc, 0x17ea44, 0x0000000f, i);
+	nv_wr32(ltc, 0x17ea48, color[0]);
+	nv_wr32(ltc, 0x17ea4c, color[1]);
+	nv_wr32(ltc, 0x17ea50, color[2]);
+	nv_wr32(ltc, 0x17ea54, color[3]);
 }
 
 void
-gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth)
+gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth)
 {
-	nv_mask(priv, 0x17ea44, 0x0000000f, i);
-	nv_wr32(priv, 0x17ea58, depth);
+	nv_mask(ltc, 0x17ea44, 0x0000000f, i);
+	nv_wr32(ltc, 0x17ea58, depth);
 }
 
 static const struct nvkm_bitfield
@@ -81,51 +81,51 @@ gf100_ltc_lts_intr_name[] = {
 };
 
 static void
-gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts)
+gf100_ltc_lts_intr(struct nvkm_ltc_priv *ltc, int c, int s)
 {
-	u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400);
-	u32 intr = nv_rd32(priv, base + 0x020);
+	u32 base = 0x141000 + (c * 0x2000) + (s * 0x400);
+	u32 intr = nv_rd32(ltc, base + 0x020);
 	u32 stat = intr & 0x0000ffff;
 
 	if (stat) {
-		nv_info(priv, "LTC%d_LTS%d:", ltc, lts);
+		nv_info(ltc, "LTC%d_LTS%d:", c, s);
 		nvkm_bitfield_print(gf100_ltc_lts_intr_name, stat);
 		pr_cont("\n");
 	}
 
-	nv_wr32(priv, base + 0x020, intr);
+	nv_wr32(ltc, base + 0x020, intr);
 }
 
 void
 gf100_ltc_intr(struct nvkm_subdev *subdev)
 {
-	struct nvkm_ltc_priv *priv = (void *)subdev;
+	struct nvkm_ltc_priv *ltc = (void *)subdev;
 	u32 mask;
 
-	mask = nv_rd32(priv, 0x00017c);
+	mask = nv_rd32(ltc, 0x00017c);
 	while (mask) {
-		u32 lts, ltc = __ffs(mask);
-		for (lts = 0; lts < priv->lts_nr; lts++)
-			gf100_ltc_lts_intr(priv, ltc, lts);
-		mask &= ~(1 << ltc);
+		u32 s, c = __ffs(mask);
+		for (s = 0; s < ltc->lts_nr; s++)
+			gf100_ltc_lts_intr(ltc, c, s);
+		mask &= ~(1 << c);
 	}
 }
 
 static int
 gf100_ltc_init(struct nvkm_object *object)
 {
-	struct nvkm_ltc_priv *priv = (void *)object;
-	u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
+	struct nvkm_ltc_priv *ltc = (void *)object;
+	u32 lpg128 = !(nv_rd32(ltc, 0x100c80) & 0x00000001);
 	int ret;
 
-	ret = nvkm_ltc_init(priv);
+	ret = nvkm_ltc_init(ltc);
 	if (ret)
 		return ret;
 
-	nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
-	nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
-	nv_wr32(priv, 0x17e8d4, priv->tag_base);
-	nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
+	nv_mask(ltc, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
+	nv_wr32(ltc, 0x17e8d8, ltc->ltc_nr);
+	nv_wr32(ltc, 0x17e8d4, ltc->tag_base);
+	nv_mask(ltc, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
 	return 0;
 }
 
@@ -133,36 +133,36 @@ void
 gf100_ltc_dtor(struct nvkm_object *object)
 {
 	struct nvkm_fb *fb = nvkm_fb(object);
-	struct nvkm_ltc_priv *priv = (void *)object;
+	struct nvkm_ltc_priv *ltc = (void *)object;
 
-	nvkm_mm_fini(&priv->tags);
+	nvkm_mm_fini(&ltc->tags);
 	if (fb->ram)
-		nvkm_mm_free(&fb->vram, &priv->tag_ram);
+		nvkm_mm_free(&fb->vram, &ltc->tag_ram);
 
-	nvkm_ltc_destroy(priv);
+	nvkm_ltc_destroy(ltc);
 }
 
 /* TODO: Figure out tag memory details and drop the over-cautious allocation.
  */
 int
-gf100_ltc_init_tag_ram(struct nvkm_fb *fb, struct nvkm_ltc_priv *priv)
+gf100_ltc_init_tag_ram(struct nvkm_fb *fb, struct nvkm_ltc_priv *ltc)
 {
 	u32 tag_size, tag_margin, tag_align;
 	int ret;
 
 	/* No VRAM, no tags for now. */
 	if (!fb->ram) {
-		priv->num_tags = 0;
+		ltc->num_tags = 0;
 		goto mm_init;
 	}
 
 	/* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
-	priv->num_tags = (fb->ram->size >> 17) / 4;
-	if (priv->num_tags > (1 << 17))
-		priv->num_tags = 1 << 17; /* we have 17 bits in PTE */
-	priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */
+	ltc->num_tags = (fb->ram->size >> 17) / 4;
+	if (ltc->num_tags > (1 << 17))
+		ltc->num_tags = 1 << 17; /* we have 17 bits in PTE */
+	ltc->num_tags = (ltc->num_tags + 63) & ~63; /* round up to 64 */
 
-	tag_align = priv->ltc_nr * 0x800;
+	tag_align = ltc->ltc_nr * 0x800;
 	tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align;
 
 	/* 4 part 4 sub: 0x2000 bytes for 56 tags */
@@ -173,25 +173,25 @@ gf100_ltc_init_tag_ram(struct nvkm_fb *fb, struct nvkm_ltc_priv *priv)
 	 *
 	 * For 4 GiB of memory we'll have 8192 tags which makes 3 MiB, < 0.1 %.
 	 */
-	tag_size  = (priv->num_tags / 64) * 0x6000 + tag_margin;
+	tag_size  = (ltc->num_tags / 64) * 0x6000 + tag_margin;
 	tag_size += tag_align;
 	tag_size  = (tag_size + 0xfff) >> 12; /* round up */
 
 	ret = nvkm_mm_tail(&fb->vram, 1, 1, tag_size, tag_size, 1,
-			   &priv->tag_ram);
+			   &ltc->tag_ram);
 	if (ret) {
-		priv->num_tags = 0;
+		ltc->num_tags = 0;
 	} else {
-		u64 tag_base = ((u64)priv->tag_ram->offset << 12) + tag_margin;
+		u64 tag_base = ((u64)ltc->tag_ram->offset << 12) + tag_margin;
 
 		tag_base += tag_align - 1;
-		ret = do_div(tag_base, tag_align);
+		do_div(tag_base, tag_align);
 
-		priv->tag_base = tag_base;
+		ltc->tag_base = tag_base;
 	}
 
 mm_init:
-	ret = nvkm_mm_init(&priv->tags, 0, priv->num_tags, 1);
+	ret = nvkm_mm_init(&ltc->tags, 0, ltc->num_tags, 1);
 	return ret;
 }
 
@@ -201,28 +201,28 @@ gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	       struct nvkm_object **pobject)
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
-	struct nvkm_ltc_priv *priv;
+	struct nvkm_ltc_priv *ltc;
 	u32 parts, mask;
 	int ret, i;
 
-	ret = nvkm_ltc_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_ltc_create(parent, engine, oclass, &ltc);
+	*pobject = nv_object(ltc);
 	if (ret)
 		return ret;
 
-	parts = nv_rd32(priv, 0x022438);
-	mask = nv_rd32(priv, 0x022554);
+	parts = nv_rd32(ltc, 0x022438);
+	mask = nv_rd32(ltc, 0x022554);
 	for (i = 0; i < parts; i++) {
 		if (!(mask & (1 << i)))
-			priv->ltc_nr++;
+			ltc->ltc_nr++;
 	}
-	priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28;
+	ltc->lts_nr = nv_rd32(ltc, 0x17e8dc) >> 28;
 
-	ret = gf100_ltc_init_tag_ram(fb, priv);
+	ret = gf100_ltc_init_tag_ram(fb, ltc);
 	if (ret)
 		return ret;
 
-	nv_subdev(priv)->intr = gf100_ltc_intr;
+	nv_subdev(ltc)->intr = gf100_ltc_intr;
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c

@@ -26,18 +26,18 @@
 static int
 gk104_ltc_init(struct nvkm_object *object)
 {
-	struct nvkm_ltc_priv *priv = (void *)object;
-	u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
+	struct nvkm_ltc_priv *ltc = (void *)object;
+	u32 lpg128 = !(nv_rd32(ltc, 0x100c80) & 0x00000001);
 	int ret;
 
-	ret = nvkm_ltc_init(priv);
+	ret = nvkm_ltc_init(ltc);
 	if (ret)
 		return ret;
 
-	nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
-	nv_wr32(priv, 0x17e000, priv->ltc_nr);
-	nv_wr32(priv, 0x17e8d4, priv->tag_base);
-	nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
+	nv_wr32(ltc, 0x17e8d8, ltc->ltc_nr);
+	nv_wr32(ltc, 0x17e000, ltc->ltc_nr);
+	nv_wr32(ltc, 0x17e8d4, ltc->tag_base);
+	nv_mask(ltc, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c

@@ -27,81 +27,81 @@
 #include <subdev/timer.h>
 
 static void
-gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
+gm107_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit)
 {
-	nv_wr32(priv, 0x17e270, start);
-	nv_wr32(priv, 0x17e274, limit);
-	nv_wr32(priv, 0x17e26c, 0x00000004);
+	nv_wr32(ltc, 0x17e270, start);
+	nv_wr32(ltc, 0x17e274, limit);
+	nv_wr32(ltc, 0x17e26c, 0x00000004);
 }
 
 static void
-gm107_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
+gm107_ltc_cbc_wait(struct nvkm_ltc_priv *ltc)
 {
 	int c, s;
-	for (c = 0; c < priv->ltc_nr; c++) {
-		for (s = 0; s < priv->lts_nr; s++)
-			nv_wait(priv, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0);
+	for (c = 0; c < ltc->ltc_nr; c++) {
+		for (s = 0; s < ltc->lts_nr; s++)
+			nv_wait(ltc, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0);
 	}
 }
 
 static void
-gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4])
+gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4])
 {
-	nv_mask(priv, 0x17e338, 0x0000000f, i);
-	nv_wr32(priv, 0x17e33c, color[0]);
-	nv_wr32(priv, 0x17e340, color[1]);
-	nv_wr32(priv, 0x17e344, color[2]);
-	nv_wr32(priv, 0x17e348, color[3]);
+	nv_mask(ltc, 0x17e338, 0x0000000f, i);
+	nv_wr32(ltc, 0x17e33c, color[0]);
+	nv_wr32(ltc, 0x17e340, color[1]);
+	nv_wr32(ltc, 0x17e344, color[2]);
+	nv_wr32(ltc, 0x17e348, color[3]);
 }
 
 static void
-gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth)
+gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth)
 {
-	nv_mask(priv, 0x17e338, 0x0000000f, i);
-	nv_wr32(priv, 0x17e34c, depth);
+	nv_mask(ltc, 0x17e338, 0x0000000f, i);
+	nv_wr32(ltc, 0x17e34c, depth);
 }
 
 static void
-gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
+gm107_ltc_lts_isr(struct nvkm_ltc_priv *ltc, int c, int s)
 {
-	u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400);
-	u32 stat = nv_rd32(priv, base + 0x00c);
+	u32 base = 0x140000 + (c * 0x2000) + (s * 0x400);
+	u32 stat = nv_rd32(ltc, base + 0x00c);
 
 	if (stat) {
-		nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", ltc, lts, stat);
-		nv_wr32(priv, base + 0x00c, stat);
+		nv_info(ltc, "LTC%d_LTS%d: 0x%08x\n", c, s, stat);
+		nv_wr32(ltc, base + 0x00c, stat);
 	}
 }
 
 static void
 gm107_ltc_intr(struct nvkm_subdev *subdev)
 {
-	struct nvkm_ltc_priv *priv = (void *)subdev;
+	struct nvkm_ltc_priv *ltc = (void *)subdev;
 	u32 mask;
 
-	mask = nv_rd32(priv, 0x00017c);
+	mask = nv_rd32(ltc, 0x00017c);
 	while (mask) {
-		u32 lts, ltc = __ffs(mask);
-		for (lts = 0; lts < priv->lts_nr; lts++)
-			gm107_ltc_lts_isr(priv, ltc, lts);
-		mask &= ~(1 << ltc);
+		u32 s, c = __ffs(mask);
+		for (s = 0; s < ltc->lts_nr; s++)
+			gm107_ltc_lts_isr(ltc, c, s);
+		mask &= ~(1 << c);
 	}
 }
 
 static int
 gm107_ltc_init(struct nvkm_object *object)
 {
-	struct nvkm_ltc_priv *priv = (void *)object;
-	u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
+	struct nvkm_ltc_priv *ltc = (void *)object;
+	u32 lpg128 = !(nv_rd32(ltc, 0x100c80) & 0x00000001);
 	int ret;
 
-	ret = nvkm_ltc_init(priv);
+	ret = nvkm_ltc_init(ltc);
 	if (ret)
 		return ret;
 
-	nv_wr32(priv, 0x17e27c, priv->ltc_nr);
-	nv_wr32(priv, 0x17e278, priv->tag_base);
-	nv_mask(priv, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
+	nv_wr32(ltc, 0x17e27c, ltc->ltc_nr);
+	nv_wr32(ltc, 0x17e278, ltc->tag_base);
+	nv_mask(ltc, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
 	return 0;
 }
 
@@ -111,24 +111,24 @@ gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	       struct nvkm_object **pobject)
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
-	struct nvkm_ltc_priv *priv;
+	struct nvkm_ltc_priv *ltc;
 	u32 parts, mask;
 	int ret, i;
 
-	ret = nvkm_ltc_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_ltc_create(parent, engine, oclass, &ltc);
+	*pobject = nv_object(ltc);
 	if (ret)
 		return ret;
 
-	parts = nv_rd32(priv, 0x022438);
-	mask = nv_rd32(priv, 0x021c14);
+	parts = nv_rd32(ltc, 0x022438);
+	mask = nv_rd32(ltc, 0x021c14);
 	for (i = 0; i < parts; i++) {
 		if (!(mask & (1 << i)))
-			priv->ltc_nr++;
+			ltc->ltc_nr++;
 	}
-	priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28;
+	ltc->lts_nr = nv_rd32(ltc, 0x17e280) >> 28;
 
-	ret = gf100_ltc_init_tag_ram(fb, priv);
+	ret = gf100_ltc_init_tag_ram(fb, ltc);
 	if (ret)
 		return ret;