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@@ -332,11 +332,255 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
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return 0;
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}
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-static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
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- struct drm_framebuffer *fb, int crtc_x,
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- int crtc_y, unsigned int crtc_w,
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- unsigned int crtc_h, uint32_t src_x,
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- uint32_t src_y, uint32_t src_w, uint32_t src_h)
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+static int tegra_window_plane_disable(struct drm_plane *plane)
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+{
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+ struct tegra_dc *dc = to_tegra_dc(plane->crtc);
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+ struct tegra_plane *p = to_tegra_plane(plane);
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+ u32 value;
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+
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+ if (!plane->crtc)
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+ return 0;
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+
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+ value = WINDOW_A_SELECT << p->index;
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+ tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
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+
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+ value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
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+ value &= ~WIN_ENABLE;
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+ tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
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+
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+ tegra_dc_window_commit(dc, p->index);
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+
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+ return 0;
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+}
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+
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+static void tegra_plane_destroy(struct drm_plane *plane)
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+{
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+ struct tegra_plane *p = to_tegra_plane(plane);
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+
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+ drm_plane_cleanup(plane);
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+ kfree(p);
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+}
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+
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+static const u32 tegra_primary_plane_formats[] = {
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+ DRM_FORMAT_XBGR8888,
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+ DRM_FORMAT_XRGB8888,
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+ DRM_FORMAT_RGB565,
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+};
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+
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+static int tegra_primary_plane_update(struct drm_plane *plane,
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+ struct drm_crtc *crtc,
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+ struct drm_framebuffer *fb, int crtc_x,
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+ int crtc_y, unsigned int crtc_w,
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+ unsigned int crtc_h, uint32_t src_x,
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+ uint32_t src_y, uint32_t src_w,
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+ uint32_t src_h)
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+{
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+ struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
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+ struct tegra_plane *p = to_tegra_plane(plane);
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+ struct tegra_dc *dc = to_tegra_dc(crtc);
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+ struct tegra_dc_window window;
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+ int err;
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+
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+ memset(&window, 0, sizeof(window));
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+ window.src.x = src_x >> 16;
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+ window.src.y = src_y >> 16;
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+ window.src.w = src_w >> 16;
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+ window.src.h = src_h >> 16;
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+ window.dst.x = crtc_x;
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+ window.dst.y = crtc_y;
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+ window.dst.w = crtc_w;
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+ window.dst.h = crtc_h;
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+ window.format = tegra_dc_format(fb->pixel_format, &window.swap);
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+ window.bits_per_pixel = fb->bits_per_pixel;
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+ window.bottom_up = tegra_fb_is_bottom_up(fb);
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+
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+ err = tegra_fb_get_tiling(fb, &window.tiling);
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+ if (err < 0)
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+ return err;
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+
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+ window.base[0] = bo->paddr + fb->offsets[0];
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+ window.stride[0] = fb->pitches[0];
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+
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+ err = tegra_dc_setup_window(dc, p->index, &window);
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+ if (err < 0)
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+ return err;
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+
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+ return 0;
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+}
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+
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+static void tegra_primary_plane_destroy(struct drm_plane *plane)
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+{
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+ tegra_window_plane_disable(plane);
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+ tegra_plane_destroy(plane);
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+}
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+
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+static const struct drm_plane_funcs tegra_primary_plane_funcs = {
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+ .update_plane = tegra_primary_plane_update,
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+ .disable_plane = tegra_window_plane_disable,
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+ .destroy = tegra_primary_plane_destroy,
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+};
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+
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+static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
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+ struct tegra_dc *dc)
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+{
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+ struct tegra_plane *plane;
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+ unsigned int num_formats;
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+ const u32 *formats;
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+ int err;
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+
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+ plane = kzalloc(sizeof(*plane), GFP_KERNEL);
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+ if (!plane)
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+ return ERR_PTR(-ENOMEM);
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+
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+ num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
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+ formats = tegra_primary_plane_formats;
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+
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+ err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
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+ &tegra_primary_plane_funcs, formats,
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+ num_formats, DRM_PLANE_TYPE_PRIMARY);
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+ if (err < 0) {
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+ kfree(plane);
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+ return ERR_PTR(err);
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+ }
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+
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+ return &plane->base;
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+}
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+
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+static const u32 tegra_cursor_plane_formats[] = {
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+ DRM_FORMAT_RGBA8888,
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+};
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+
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+static int tegra_cursor_plane_update(struct drm_plane *plane,
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+ struct drm_crtc *crtc,
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+ struct drm_framebuffer *fb, int crtc_x,
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+ int crtc_y, unsigned int crtc_w,
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+ unsigned int crtc_h, uint32_t src_x,
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+ uint32_t src_y, uint32_t src_w,
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+ uint32_t src_h)
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+{
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+ struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
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+ struct tegra_dc *dc = to_tegra_dc(crtc);
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+ u32 value = CURSOR_CLIP_DISPLAY;
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+
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+ /* scaling not supported for cursor */
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+ if ((src_w >> 16 != crtc_w) || (src_h >> 16 != crtc_h))
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+ return -EINVAL;
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+
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+ /* only square cursors supported */
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+ if (src_w != src_h)
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+ return -EINVAL;
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+
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+ switch (crtc_w) {
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+ case 32:
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+ value |= CURSOR_SIZE_32x32;
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+ break;
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+
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+ case 64:
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+ value |= CURSOR_SIZE_64x64;
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+ break;
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+
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+ case 128:
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+ value |= CURSOR_SIZE_128x128;
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+ break;
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+
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+ case 256:
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+ value |= CURSOR_SIZE_256x256;
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+ break;
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+
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ value |= (bo->paddr >> 10) & 0x3fffff;
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+ tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
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+
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+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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+ value = (bo->paddr >> 32) & 0x3;
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+ tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
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+#endif
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+
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+ /* enable cursor and set blend mode */
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+ value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
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+ value |= CURSOR_ENABLE;
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+ tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
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+
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+ value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
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+ value &= ~CURSOR_DST_BLEND_MASK;
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+ value &= ~CURSOR_SRC_BLEND_MASK;
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+ value |= CURSOR_MODE_NORMAL;
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+ value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
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+ value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
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+ value |= CURSOR_ALPHA;
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+ tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
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+
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+ /* position the cursor */
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+ value = (crtc_y & 0x3fff) << 16 | (crtc_x & 0x3fff);
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+ tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
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+
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+ /* apply changes */
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+ tegra_dc_cursor_commit(dc);
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+ tegra_dc_commit(dc);
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+
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+ return 0;
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+}
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+
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+static int tegra_cursor_plane_disable(struct drm_plane *plane)
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+{
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+ struct tegra_dc *dc = to_tegra_dc(plane->crtc);
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+ u32 value;
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+
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+ if (!plane->crtc)
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+ return 0;
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+
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+ value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
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+ value &= ~CURSOR_ENABLE;
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+ tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
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+
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+ tegra_dc_cursor_commit(dc);
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+ tegra_dc_commit(dc);
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+
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+ return 0;
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+}
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+
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+static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
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+ .update_plane = tegra_cursor_plane_update,
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+ .disable_plane = tegra_cursor_plane_disable,
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+ .destroy = tegra_plane_destroy,
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+};
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+
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+static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
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+ struct tegra_dc *dc)
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+{
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+ struct tegra_plane *plane;
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+ unsigned int num_formats;
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+ const u32 *formats;
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+ int err;
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+
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+ plane = kzalloc(sizeof(*plane), GFP_KERNEL);
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+ if (!plane)
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+ return ERR_PTR(-ENOMEM);
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+
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+ num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
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+ formats = tegra_cursor_plane_formats;
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+
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+ err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
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+ &tegra_cursor_plane_funcs, formats,
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+ num_formats, DRM_PLANE_TYPE_CURSOR);
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+ if (err < 0) {
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+ kfree(plane);
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+ return ERR_PTR(err);
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+ }
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+
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+ return &plane->base;
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+}
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+
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+static int tegra_overlay_plane_update(struct drm_plane *plane,
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+ struct drm_crtc *crtc,
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+ struct drm_framebuffer *fb, int crtc_x,
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+ int crtc_y, unsigned int crtc_w,
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+ unsigned int crtc_h, uint32_t src_x,
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+ uint32_t src_y, uint32_t src_w,
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+ uint32_t src_h)
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{
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struct tegra_plane *p = to_tegra_plane(plane);
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struct tegra_dc *dc = to_tegra_dc(crtc);
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@@ -382,43 +626,19 @@ static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
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return tegra_dc_setup_window(dc, p->index, &window);
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}
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-static int tegra_plane_disable(struct drm_plane *plane)
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-{
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- struct tegra_dc *dc = to_tegra_dc(plane->crtc);
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- struct tegra_plane *p = to_tegra_plane(plane);
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- unsigned long value;
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-
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- if (!plane->crtc)
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- return 0;
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-
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- value = WINDOW_A_SELECT << p->index;
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- tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
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-
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- value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
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- value &= ~WIN_ENABLE;
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- tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
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-
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- tegra_dc_window_commit(dc, p->index);
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-
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- return 0;
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-}
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-
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-static void tegra_plane_destroy(struct drm_plane *plane)
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+static void tegra_overlay_plane_destroy(struct drm_plane *plane)
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{
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- struct tegra_plane *p = to_tegra_plane(plane);
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-
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- tegra_plane_disable(plane);
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- drm_plane_cleanup(plane);
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- kfree(p);
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+ tegra_window_plane_disable(plane);
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+ tegra_plane_destroy(plane);
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}
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-static const struct drm_plane_funcs tegra_plane_funcs = {
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- .update_plane = tegra_plane_update,
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- .disable_plane = tegra_plane_disable,
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- .destroy = tegra_plane_destroy,
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+static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
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+ .update_plane = tegra_overlay_plane_update,
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+ .disable_plane = tegra_window_plane_disable,
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+ .destroy = tegra_overlay_plane_destroy,
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};
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-static const uint32_t plane_formats[] = {
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+static const uint32_t tegra_overlay_plane_formats[] = {
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_RGB565,
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@@ -428,27 +648,44 @@ static const uint32_t plane_formats[] = {
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DRM_FORMAT_YUV422,
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};
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-static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
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+static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
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+ struct tegra_dc *dc,
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+ unsigned int index)
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{
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- unsigned int i;
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- int err = 0;
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+ struct tegra_plane *plane;
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+ unsigned int num_formats;
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+ const u32 *formats;
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+ int err;
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- for (i = 0; i < 2; i++) {
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- struct tegra_plane *plane;
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+ plane = kzalloc(sizeof(*plane), GFP_KERNEL);
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+ if (!plane)
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+ return ERR_PTR(-ENOMEM);
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- plane = kzalloc(sizeof(*plane), GFP_KERNEL);
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- if (!plane)
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- return -ENOMEM;
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+ plane->index = index;
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- plane->index = 1 + i;
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+ num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
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+ formats = tegra_overlay_plane_formats;
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- err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
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- &tegra_plane_funcs, plane_formats,
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- ARRAY_SIZE(plane_formats), false);
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- if (err < 0) {
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- kfree(plane);
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- return err;
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- }
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+ err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
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+ &tegra_overlay_plane_funcs, formats,
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+ num_formats, DRM_PLANE_TYPE_OVERLAY);
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+ if (err < 0) {
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+ kfree(plane);
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+ return ERR_PTR(err);
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+ }
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+
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+ return &plane->base;
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+}
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+
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+static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
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+{
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+ struct drm_plane *plane;
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+ unsigned int i;
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+
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+ for (i = 0; i < 2; i++) {
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+ plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
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+ if (IS_ERR(plane))
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+ return PTR_ERR(plane);
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}
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return 0;
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@@ -568,103 +805,6 @@ void tegra_dc_disable_vblank(struct tegra_dc *dc)
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spin_unlock_irqrestore(&dc->lock, flags);
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}
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-static int tegra_dc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file,
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- uint32_t handle, uint32_t width,
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- uint32_t height, int32_t hot_x, int32_t hot_y)
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-{
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- unsigned long value = CURSOR_CLIP_DISPLAY;
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- struct tegra_dc *dc = to_tegra_dc(crtc);
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- struct drm_gem_object *gem;
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- struct tegra_bo *bo = NULL;
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-
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- if (!dc->soc->supports_cursor)
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- return -ENXIO;
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-
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- if (width != height)
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- return -EINVAL;
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-
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- switch (width) {
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- case 32:
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- value |= CURSOR_SIZE_32x32;
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|
- break;
|
|
|
-
|
|
|
- case 64:
|
|
|
- value |= CURSOR_SIZE_64x64;
|
|
|
- break;
|
|
|
-
|
|
|
- case 128:
|
|
|
- value |= CURSOR_SIZE_128x128;
|
|
|
-
|
|
|
- case 256:
|
|
|
- value |= CURSOR_SIZE_256x256;
|
|
|
- break;
|
|
|
-
|
|
|
- default:
|
|
|
- return -EINVAL;
|
|
|
- }
|
|
|
-
|
|
|
- if (handle) {
|
|
|
- gem = drm_gem_object_lookup(crtc->dev, file, handle);
|
|
|
- if (!gem)
|
|
|
- return -ENOENT;
|
|
|
-
|
|
|
- bo = to_tegra_bo(gem);
|
|
|
- }
|
|
|
-
|
|
|
- if (bo) {
|
|
|
- unsigned long addr = (bo->paddr & 0xfffffc00) >> 10;
|
|
|
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
|
|
|
- unsigned long high = (bo->paddr & 0xfffffffc) >> 32;
|
|
|
-#endif
|
|
|
-
|
|
|
- tegra_dc_writel(dc, value | addr, DC_DISP_CURSOR_START_ADDR);
|
|
|
-
|
|
|
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
|
|
|
- tegra_dc_writel(dc, high, DC_DISP_CURSOR_START_ADDR_HI);
|
|
|
-#endif
|
|
|
-
|
|
|
- value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
|
|
- value |= CURSOR_ENABLE;
|
|
|
- tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
|
|
-
|
|
|
- value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
|
|
|
- value &= ~CURSOR_DST_BLEND_MASK;
|
|
|
- value &= ~CURSOR_SRC_BLEND_MASK;
|
|
|
- value |= CURSOR_MODE_NORMAL;
|
|
|
- value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
|
|
|
- value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
|
|
|
- value |= CURSOR_ALPHA;
|
|
|
- tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
|
|
|
- } else {
|
|
|
- value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
|
|
- value &= ~CURSOR_ENABLE;
|
|
|
- tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
|
|
- }
|
|
|
-
|
|
|
- tegra_dc_cursor_commit(dc);
|
|
|
- tegra_dc_commit(dc);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-static int tegra_dc_cursor_move(struct drm_crtc *crtc, int x, int y)
|
|
|
-{
|
|
|
- struct tegra_dc *dc = to_tegra_dc(crtc);
|
|
|
- unsigned long value;
|
|
|
-
|
|
|
- if (!dc->soc->supports_cursor)
|
|
|
- return -ENXIO;
|
|
|
-
|
|
|
- value = ((y & 0x3fff) << 16) | (x & 0x3fff);
|
|
|
- tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
|
|
|
-
|
|
|
- tegra_dc_cursor_commit(dc);
|
|
|
- /* XXX: only required on generations earlier than Tegra124? */
|
|
|
- tegra_dc_commit(dc);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
|
|
|
{
|
|
|
struct drm_device *drm = dc->base.dev;
|
|
@@ -741,8 +881,6 @@ static void tegra_dc_destroy(struct drm_crtc *crtc)
|
|
|
}
|
|
|
|
|
|
static const struct drm_crtc_funcs tegra_crtc_funcs = {
|
|
|
- .cursor_set2 = tegra_dc_cursor_set2,
|
|
|
- .cursor_move = tegra_dc_cursor_move,
|
|
|
.page_flip = tegra_dc_page_flip,
|
|
|
.set_config = drm_crtc_helper_set_config,
|
|
|
.destroy = tegra_dc_destroy,
|
|
@@ -756,7 +894,7 @@ static void tegra_crtc_disable(struct drm_crtc *crtc)
|
|
|
|
|
|
drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
|
|
|
if (plane->crtc == crtc) {
|
|
|
- tegra_plane_disable(plane);
|
|
|
+ tegra_window_plane_disable(plane);
|
|
|
plane->crtc = NULL;
|
|
|
|
|
|
if (plane->fb) {
|
|
@@ -767,6 +905,7 @@ static void tegra_crtc_disable(struct drm_crtc *crtc)
|
|
|
}
|
|
|
|
|
|
drm_vblank_off(drm, dc->pipe);
|
|
|
+ tegra_dc_commit(dc);
|
|
|
}
|
|
|
|
|
|
static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
@@ -1293,6 +1432,8 @@ static int tegra_dc_init(struct host1x_client *client)
|
|
|
struct drm_device *drm = dev_get_drvdata(client->parent);
|
|
|
struct tegra_dc *dc = host1x_client_to_dc(client);
|
|
|
struct tegra_drm *tegra = drm->dev_private;
|
|
|
+ struct drm_plane *primary = NULL;
|
|
|
+ struct drm_plane *cursor = NULL;
|
|
|
int err;
|
|
|
|
|
|
if (tegra->domain) {
|
|
@@ -1306,7 +1447,25 @@ static int tegra_dc_init(struct host1x_client *client)
|
|
|
dc->domain = tegra->domain;
|
|
|
}
|
|
|
|
|
|
- drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
|
|
|
+ primary = tegra_dc_primary_plane_create(drm, dc);
|
|
|
+ if (IS_ERR(primary)) {
|
|
|
+ err = PTR_ERR(primary);
|
|
|
+ goto cleanup;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (dc->soc->supports_cursor) {
|
|
|
+ cursor = tegra_dc_cursor_plane_create(drm, dc);
|
|
|
+ if (IS_ERR(cursor)) {
|
|
|
+ err = PTR_ERR(cursor);
|
|
|
+ goto cleanup;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
|
|
|
+ &tegra_crtc_funcs);
|
|
|
+ if (err < 0)
|
|
|
+ goto cleanup;
|
|
|
+
|
|
|
drm_mode_crtc_set_gamma_size(&dc->base, 256);
|
|
|
drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
|
|
|
|
|
@@ -1320,12 +1479,12 @@ static int tegra_dc_init(struct host1x_client *client)
|
|
|
err = tegra_dc_rgb_init(drm, dc);
|
|
|
if (err < 0 && err != -ENODEV) {
|
|
|
dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
|
|
|
- return err;
|
|
|
+ goto cleanup;
|
|
|
}
|
|
|
|
|
|
err = tegra_dc_add_planes(drm, dc);
|
|
|
if (err < 0)
|
|
|
- return err;
|
|
|
+ goto cleanup;
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
|
|
|
err = tegra_dc_debugfs_init(dc, drm->primary);
|
|
@@ -1338,10 +1497,24 @@ static int tegra_dc_init(struct host1x_client *client)
|
|
|
if (err < 0) {
|
|
|
dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
|
|
|
err);
|
|
|
- return err;
|
|
|
+ goto cleanup;
|
|
|
}
|
|
|
|
|
|
return 0;
|
|
|
+
|
|
|
+cleanup:
|
|
|
+ if (cursor)
|
|
|
+ drm_plane_cleanup(cursor);
|
|
|
+
|
|
|
+ if (primary)
|
|
|
+ drm_plane_cleanup(primary);
|
|
|
+
|
|
|
+ if (tegra->domain) {
|
|
|
+ iommu_detach_device(tegra->domain, dc->dev);
|
|
|
+ dc->domain = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ return err;
|
|
|
}
|
|
|
|
|
|
static int tegra_dc_exit(struct host1x_client *client)
|