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drm/i915: Read the CCK fuse register from CCK

When reading a CCK register we should obviously read it from CCK not
Punit. This problem has been present ever since this of code was
introduced in

 commit 67c3bf6f55a97a0915a0f9ea07278a3073cc9601
 Author: Deepak S <deepak.s@linux.intel.com>
 Date:   Thu Jul 10 13:16:24 2014 +0530

    drm/i915: populate mem_freq/cz_clock for chv

The problem was raised during review by Mika [1] but somehow slipped
through the cracks, and the patch got applied with the problem unfixed.

[1] http://lists.freedesktop.org/archives/intel-gfx/2014-July/048937.html

Cc: Deepak S <deepak.s@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä 10 years ago
parent
commit
c6e8f39db9
1 changed files with 4 additions and 1 deletions
  1. 4 1
      drivers/gpu/drm/i915/intel_pm.c

+ 4 - 1
drivers/gpu/drm/i915/intel_pm.c

@@ -5195,7 +5195,10 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
 
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	mutex_lock(&dev_priv->rps.hw_lock);
 
 
-	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
+	mutex_lock(&dev_priv->dpio_lock);
+	val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
+	mutex_unlock(&dev_priv->dpio_lock);
+
 	switch ((val >> 2) & 0x7) {
 	switch ((val >> 2) & 0x7) {
 	case 0:
 	case 0:
 	case 1:
 	case 1: