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@@ -2535,8 +2535,6 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
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u32 val;
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int err;
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-#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
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-
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val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
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val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
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if (force_on)
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@@ -2546,13 +2544,16 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
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if (!force_on)
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return 0;
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- err = wait_for(COND, 20);
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+ err = intel_wait_for_register(dev_priv,
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+ VLV_GTLC_SURVIVABILITY_REG,
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+ VLV_GFX_CLK_STATUS_BIT,
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+ VLV_GFX_CLK_STATUS_BIT,
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+ 20);
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if (err)
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DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
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I915_READ(VLV_GTLC_SURVIVABILITY_REG));
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return err;
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-#undef COND
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}
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static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
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